TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
IOR
(RD RBR)
Active
50%
(see Note A)
SIN
(first byte)
Stop
Sample
CLK
t
d9
(see Note B )
RXRDY
t
pd8
50%
50%
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0 = 1, t = 3 RCLK cycles. For a time-out interrupt, t = 8 RCLK cycles.
d9 d9
Figure 12. Receiver Ready Mode 0 Waveforms
IOR
(RD RBR)
Active
50%
(see Note A)
SIN
(first byte that reaches
the trigger level)
Stop
Sample
CLK
t
d9
(see Note B)
50%
RXRDY
50%
t
pd8
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCR0–1, t = 3 RCLK cycles. For a trigger change level interrupt, t = 8 RCLK.
d9
d9
Figure 13. Receiver Ready Mode 1 Waveforms
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