TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
PARAMETER MEASUREMENT INFORMATION
Valid
Valid
50%
50%
A2, A1, A0
t
h3
CS0, CS1, CS2
50%
50%
t
su4
t
h4
t
d3
t
su5
Active
Active
IOW
50%
50%
50%
50%
t
d4
t
w5
or
Active
IOR
t
su6
t
h5
DB0–DB7
Valid Data
Figure 5. Write Cycle Timing Waveforms
Start
Start
50%
Serial Out
(SOUT)
Data Bits 5–8
50%
Stop (1–2)
Parity
50%
t
d5
t
d6
Interrupt
(THRE)
50%
50%
50%
50%
t
pd2
t
d7
t
pd2
IOW
(WR THR)
50%
50%
50%
t
pd4
IOR
(RD IIR)
50%
Figure 6. Transmitter Timing Waveforms
Byte #1
IOW
50%
(WR THR)
Start
Data
Parity
Stop 50%
SOUT
t
d8
t
pd5
TXRDY
50%
50%
Figure 7. Transmitter Ready Mode 0 Timing Waveforms
12
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