TL16C552A, TL16C552AM
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189D – NOVEMBER 1994 – REVISED JANUARY 1999
parallel port timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Note 16 and Figures 15, 16, and 17)
MIN
1
MAX
UNIT
µs
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, data valid before STB ↓
Hold time, data valid after STB ↑
Pulse duration, STB ↓
su7
1
µs
h6
1
µs
w6
Delay time, BUSY ↑ to ACK ↓
Defined by printer
d10
d11
w7
Delay time, BUSY ↓ to ACK ↓
Defined by printer
Pulse duration, BUSY ↑
Defined by printer
Pulse duration, ACK ↓
Defined by printer
w8
Delay time, BUSY ↑ after STB ↑
Delay time, INT2 ↓ after ACK ↓ (see Note 17)
Delay time, INT2 ↑ after ACK ↑ (see Note 17)
Delay time, INT2 ↑ after ACK ↑ (see Note 17)
Delay time, INT2 ↓ after IOR ↑ (see Note 17)
Defined by printer
d12
d13
d14
d15
d16
22
20
24
25
ns
ns
ns
ns
NOTES: 16. These parameters are not production tested.
17. –t are all measured with a 15-pF load.
t
d13 d16
PARAMETER MEASUREMENT INFORMATION
t
w1
2 V
2 V
0.8 V
CLK (XTAL1)
0.8 V
t
w2
f
= 16 MHz MAX
clock
Figure 1. CLK Voltage Waveform
2.54 V
Device Under Test
680 Ω
TL16C552A
82 pF
(see Note A)
NOTE A: This includes scope and jig capacitance.
Figure 2. Output Load Circuit
10
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