TAS5614LA
SLAS846 –MAY 2012
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
TAS5614LA
–0.3 to 13.2
–0.3 to 50
–0.3 to 62.5
–0.3 to 4.2
–0.3 to 8.5
–0.3 to 4.2
–0.3 to 4.2
9
UNIT
V
VDD to GND, GVDD_X(2) to GND
PVDD_X(2) to GND(3), OUT_X to GND(3), BST_X to GVDD_X(2)(3)
BST_X to GND(3)(4)
V
V
DVDD to GND
V
AVDD to GND
V
OC_ADJ, M1, M2, M3, C_START, INPUT_X to GND
RESET, FAULT, OTW, CLIP, to GND
Maximum continuous sink current (FAULT, OTW, CLIP)
Maximum operating junction temperature range, TJ
Storage temperature, Tstg
V
V
mA
°C
°C
°C
kV
V
0 to 150
–40 to 150
260
Lead temperature
Human body model(4) (all pins)
Charged device model(4) (all pins)
±2
Electrostatic discharge
±500
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) GVDD_X and PVDD_X represents a full bridge gate drive or power supply. GVDD_X is GVDD_AB or GVDD_CD, PVDD_X is
PVDD_AB or PVDD_CD
(3) These voltages represents the DC voltage + peak AC waveform measured at the terminal of the device in all conditions.
(4) Maximum BST_X to GND voltage is the sum of maximum PVDD to GND and GVDD to GND voltages minus a diode drop.
THERMAL INFORMATION
TAS5614LA
THERMAL METRIC(1)
UNITS
DDV (44-PIN)
θJH
Junction-to-heat sink thermal resistance(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
2.3
0.8
2.1
0.8
2.1
n/a
θJCtop
θJB
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
θJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) Thermal data are obtained with 85°C heat sink temperature using thermal compound with 0.7W/mK thermal conductivity and 2mil
thickness.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP MAX UNIT
PVDD_X
GVDD_X
VDD
Full-bridge supply
DC supply voltage
DC supply voltage
DC supply voltage
12
36
38
V
V
V
Supply for logic regulators and gate-drive
circuitry
10.8
12 13.2
Digital regulator supply voltage
BTL
10.8
3.0
1.5
1.5
12 13.2
4.0
Output filter: L = 10 µH, 1 µF.
Output AD modulation,
switching frequency > 350 kHz.
RL
Load impedance
SE
3.0
Ω
PBTL
2.0
Minimum inductance at overcurrent limit,
including inductor tolerance, temperature
and possible inductor saturation
LOUTPUT
Output filter inductance
PWM frame rate
5
μH
FPWM
352
384 500 kHz
CPVDD
PVDD close decoupling capacitors
0.44
1
100
1
μF
nF
μF
BTL and PBTL configuration
C_START
Startup ramp capacitor
SE and 1xBTL+2xSE configuration
4
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