TAS5614LA
www.ti.com
SLAS846 –MAY 2012
AUDIO SPECIFICATION MONO (PBTL)
Audio performance is recorded as a chipset consisting of a TASxxxx PWM Processor (modulation index limited to 97.7%) and
a TAS5614LA power stage with PCB and system configurations in accordance with recommended guidelines. Audio
frequency = 1kHz, PVDD_X = 36V, GVDD_X = 12V, RL = 4Ω, fS = 384kHz, ROC = 24kΩ, TC = 75°C, Output Filter: LDEM
10μH, CDEM = 1μF, unless otherwise noted.
=
PARAMETER
TEST CONDITIONS
RL = 2 Ω, 10%, THD+N
MIN
TYP MAX UNIT
300
200
RL = 3 Ω, 10% THD+N
RL = 4 Ω, 10% THD+N
RL = 2 Ω, 1% THD+N
160
PO
Power output per channel
W
250
RL = 3 Ω, 1% THD+N
160
130
RL = 4 Ω, 1% THD+N
THD+N
Vn
Total harmonic distortion + noise
Output integrated noise
Output offset voltage
Signal to noise ratio(1)
Dynamic range
1 W, 1 kHz signal
0.025
180
10
%
μV
mV
dB
dB
A-weighted, AES17 measuring filter
No signal
VOS
20
SNR
DNR
A-weighted, AES17 measuring filter
A-weighted, –60 dBFS (rel 1% THD)
105
105
Power dissipation due to idle losses
(IPVDD_X)
Pidle
PO = 0, All channels switching(2)
1.6
W
(1) SNR is calculated relative to 1% THD-N output level.
(2) Actual system idle losses are affected by core losses of output inductors.
ELECTRICAL CHARACTERISTICS
PVDD_X = 36 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL VOLTAGE REGULATOR AND CURRENT CONSUMPTION
Voltage regulator, only used as a
DVDD
VDD = 12 V
3.0
3.3
7.8
3.6
V
V
reference node
Voltage regulator, only used as a
reference node
AVDD
VDD = 12 V
Operating, 50% duty cycle
Idle, reset mode
20
20
IVDD
VDD supply current
mA
mA
50% duty cycle
9
IGVDD_X
Gate-supply current per full-bridge
Reset mode
2
50% duty cycle without load
RESET low
23
IPVDD_X
Full-bridge idle current
1.9
0.35
mA
VDD and GVDD_X at 0V
OUTPUT-STAGE MOSFETs
Drain-to-source resistance, low side
RDS(on), LS
60
60
100
100
mΩ
mΩ
(LS)
TJ = 25°C, excludes metalization resistance,
GVDD = 12 V
Drain-to-source resistance, high side
(HS)
RDS(on), HS
I/O PROTECTION
Vuvp,GVDD
8.5
0.7
8.5
0.7
8.5
0.7
125
V
V
Undervoltage protection limit, GVDD_X
Undervoltage protection limit, VDD
(1)
Vuvp,GVDD, hyst
Vuvp,VDD
V
(1)
Vuvp,VDD, hyst
V
Vuvp,PVDD
V
Undervoltage protection limit, PVDD_X
Overtemperature warning
(1)
Vuvp,PVDD,hyst
OTW(1)
V
115
145
135
165
°C
Temperature drop needed below OTW
temperature for OTW to be inactive
after OTW event.
(1)
OTWhyst
25
°C
°C
OTE(1)
Overtemperature error
155
(1) Specified by design.
Copyright © 2012, Texas Instruments Incorporated
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