ꢀ ꢁꢂ ꢃꢄ ꢅꢆ ꢃꢅ
ꢇꢈ ꢉꢈ ꢊꢋꢌ ꢀꢈ ꢉ ꢍꢋꢌ ꢎꢏ ꢐ ꢆꢑ ꢀ ꢀꢐ ꢏ
SOURCED FROM: SGUS014H − FEBRUARY 1991 − REVISED JUNE 2004
timer pin (TCLK0 and TCLK1) timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers.
The following table defines the timing parameters for the timer pin.
timing parameters for timer pin (TCLK0 and TCLK1) (see Figure 29)
‡
‡
320C30-40
320C30-50
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time,
TCLK ext
before H1 low
99
t
t
t
TCLK ext
10
0
8
0
ns
su(TCLK-H1L)
h(TCLK-H1L)
d(TCLK-H1H)
Hold time,
TCLK ext after TCLK ext
H1 low
100
101
ns
ns
Delay time, H1
high to TCLK
int valid
TCLK int
9
9
TCLK ext
TCLK int
TCLK ext
TCLK int
t
× 2.6*
t
× 2.6*
ns
ns
ns
ns
c(H)
c(H)
Cycle time,
TCLK
102
103
t
t
c(TCLK)
32
× 2
32
× 2 *
t
× 2
t
*
t
× 2
t
c(H)
c(H)
c(H)
c(H)
t
+ 12*
t
+ 10*
c(H)
c(H)
Pulse duration,
TCLK high/low
w(TCLK)
[t
c(TCLK)
/2]−5 [t
/2]+5
[t
c(TCLK)
/2]−5 [t
/2]+5
c(TCLK)
c(TCLK)
†
‡
Numbers in this column are used in Figure 29.
Timing parameters 99 and 100 are applicable for a synchronous input clock. Timing parameters 102 and 103 are applicable for an asynchronous
input clock.
* This parameter is not production tested.
H3
H1
100
101
103
101
99
Timer
Pin
102
NOTE A: Period and polarity of valid logic level are specified by contents of internal control registers.
Figure 29. Timing for Timer Pin
39
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