RM48L950
RM48L750
RM48L550
www.ti.com
SPNS174–SEPTEMBER 2011
1.4 Functional Block Diagram
Color Legend for Power Domains
RAM
Core/RAM
Core
always on
# 1
# 2
# 3
# 4
# 5
# 1
# 2
64K
3M
256K
64K RAM
with
Flash
with
ECC
# 3
64K
ECC
64K
ETM-R4
RTP
DMA
POM
DMM
HTU1 HTU2
EMAC
USB Host
Dual Cortex-R4F
CPUs in Lockstep
Switched Central Resource Switched Central Resource Switched Central Resource
Main Cross Bar: Arbitration and Prioritization Control
64 KB Flash
Peripheral Central Resource Bridge
CRC Switched Central Resource
for EEPROM
Emulation
with ECC
nPORRST
nRST
SYS
ECLK
IOMM
EMAC Slaves
USB Slaves
nERROR
ESM
MDCLK
MDIO
USB1.OverCurrent
USB1.RCV
USB1.VM
PMM
CAN1_RX
CAN1_TX
CAN2_RX
CAN2_TX
CAN3_RX
CAN3_TX
MDIO
MII
DCAN1
MII_RXD[3:0]
MII_RXER
MII_TXD[3:0]
MII_TXEN
MII_TXCLK
MII_RXCLK
USB1.VP
DCAN2
VIM
USB1.PortPower
USB1.SPEED
USB1.SUSPEND
USB1.TXDAT
USB1.TXEN
USB1.TXSE0
USB2.OverCurrent
USB2.RCV
DCAN3
MIBSPI1_CLK
MIBSPI1_SIMO[1:0]
MIBSPI1_SOMI[1:0]
MII_CRS
MII_RXDV
MII_COL
Host
MibSPI1
RTI
MIBSPI1_nCS[5:0]
MIBSPI1_nENA
USB2.VM
USB2.VP
SPI2_CLK
SPI2_SIMO
SPI2_SOMI
EMIF_nWAIT
EMIF_CLK
USB2.PortPower
USB2.SPEED
USB2.SUSPEND
USB2.TXDAT
USB2.TXEN
DCC1
DCC2
SPI2
MibSPI3
SPI4
EMIF_CKE
SPI2_nCS[1:0]
SPI2_nENA
EMIF_nCS[4:2]
EMIF_nCS[0]
EMIF_ADDR[21:0]
EMIF_BA[1:0]
EMIF_DATA[15:0]
EMIF_nDQM[1:0]
EMIF_nOE
MIBSPI3_CLK
USB2.TXSE0
MIBSPI3_SIMO
MIBSPI3_SOMI
MIBSPI3_nCS[5:0]
MIBSPI3_nENA
USB_FUNC.GZO
EMIF
USB_FUNC.PUENO
USB_FUNC.PUENON
USB_FUNC.RXDI
USB_FUNC.RXDMI
USB_FUNC.RXDPI
USB_FUNC.SE0O
USB_FUNC.SUSPENDO
USB_FUNC.TXDO
USB_FUNC.VBUSI
SPI4_CLK
Device
EMIF_nWE
SPI4_SIMO
SPI4_SOMI
SPI4_nCS0
SPI4_nENA
EMIF_nRAS
EMIF_nCAS
EMIF_nRW
MIBSPI5_SIMO[3:0]
MIBSPI5_SOMI[3:0]
MIBSPI5_nCS[3:0]
MIBSPI5_nENA
MibSPI5
MibADC1
MibADC2
N2HET1 N2HET2 GIO
I2C
LIN_RX
LIN_TX
LIN
SCI
SCI_RX
SCI_TX
Figure 1-1. Functional Block Diagram
Copyright © 2011, Texas Instruments Incorporated
RM48Lx50 16/32-Bit RISC Flash Microcontroller
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