RM48L950
RM48L750
RM48L550
www.ti.com
SPNS174–SEPTEMBER 2011
1.3 Description
The RM48Lx50 is a high performance microcontroller family for safety systems. The safety architecture
includes Dual CPUs in lockstep, CPU and Memory Built-In Self Test (BIST) logic, ECC on both the Flash
and the data SRAM, parity on peripheral memories, and loop back capability on peripheral IOs.
The RM48Lx50 integrates the ARM® Cortex™-R4F Floating Point CPU which offers an efficient 1.6
DMIPS/MHz, and has configurations which can run up to 200MHz providing up to 320 DMIPS. The device
supports the little-endian [LE32] format.
The RM48Lx50 has up to 3MB integrated Flash and up to 256KB data RAM configurations with single bit
error correction and double bit error detection. The flash memory on this device is a nonvolatile,
electrically erasable and programmable memory implemented with a 64-bit-wide data bus interface. The
flash operates on a 3.3V supply input (same level as I/O supply) for all read, program and erase
operations. When in pipeline mode, the flash operates with a system clock frequency of up to 200MHz.
The SRAM supports single-cycle read/write accesses in byte, halfword, and word modes.
The RM48Lx50 device features peripherals for real-time control-based applications, including two Next
Generation High End Timer (N2HET) timing coprocessors with up to 44 total IO terminals and a 12-bit
Analog-to-Digital converter supporting up to 24 inputs.
The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time
applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer
micromachine and an attached I/O port. The N2HET can be used for pulse width modulated outputs,
capture or compare inputs, or general-purpose I/O. It is especially well suited for applications requiring
multiple sensor information and drive actuators with complex and accurate time pulses. A High End Timer
Transfer Unit (HET-TU) can perform DMA type transactions to transfer N2HET data to or from main
memory. A Memory Protection Unit (MPU) is built into the HET-TU.
The device has two 12-bit-resolution MibADCs with 24 total channels and 64 words of parity protected
buffer RAM each. The MibADC channels can be converted individually or can be grouped by software for
sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are
three separate groupings. Each sequence can be converted once when triggered or configured for
continuous conversion mode.
The device has multiple communication interfaces: three MibSPIs, up to two SPIs, one LIN, one SCI, three
DCANs, one I2C, one Ethernet, and one USB module.. The SPI provides a convenient method of serial
interaction for high-speed communications between similar shift-register type devices. The LIN supports
the Local Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard
Non-Return-to-Zero (NRZ) format. The DCAN supports the CAN 2.0B protocol standard and uses a serial,
multimaster communication protocol that efficiently supports distributed real-time control with robust
communication rates of up to 1 megabit per second (Mbps). The DCAN is ideal for applications operating
in noisy and harsh environments (e.g., automotive and industrial fields) that require reliable serial
communication or multiplexed wiring. The Ethernet module supports MII and MDIO interfaces. The USB
module includes a 2-port USB host controller and a USB device controller
The I2C module is a multi-master communication module providing an interface between the
microcontroller and an I2C compatible device via the I2C serial bus. The I2C supports both 100 Kbps and
400 Kbps speeds.
The frequency-modulated phase-locked loop (FMPLL) clock module is used to multiply the external
frequency reference to a higher frequency for internal use. The FMPLL provides one of the seven possible
clock source inputs to the global clock module (GCM). The GCM module manages the mapping between
the available clock sources and the device clock domains.
The device also has an external clock prescaler (ECP) module that when enabled, outputs a continuous
external clock on the ECLK pin/ball. The ECLK frequency is a user-programmable ratio of the peripheral
interface clock (VCLK) frequency. This low frequency output can be monitored externally as an indicator of
the device operating frequency.
Copyright © 2011, Texas Instruments Incorporated
RM48Lx50 16/32-Bit RISC Flash Microcontroller
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