RM48L950
RM48L750
RM48L550
www.ti.com
SPNS174–SEPTEMBER 2011
RM48Lx50 16/32-Bit RISC Flash Microcontroller
Check for Samples: RM48L950
1 RM48Lx50 16/32-Bit RISC Flash Microcontroller
1.1 Features
1
• High-Performance Microcontroller for Safety
• Multiple Communication Interfaces
– 10/100 Mbps Ethernet MAC (EMAC)
Critical Applications
– Dual CPU’s running in lockstep
– ECC on flash and RAM interfaces
•
•
IEEE 802.3 compliant (3.3V-I/O only)
Supports MII and MDIO
– Built-In Self Test for CPU and on-chip RAMs
– Error Signaling Module with Error Pin
– Voltage and Clock Monitoring
– USB
•
2-port USB Specification, revision
2.0-compatible host controller, based on
the OHCI Specification for USB, release
1.0
• ARM® Cortex™ – R4F 32-bit RISC CPU
– Efficient 1.6DMIPS/MHz with 8-stage pipeline
•
One full-speed USB device compatible
with the USB Specification, revision 2.0
and USB Specification, revision 1.1
– Floating-Point Unit with Single/Double
Precision
– 12-Region Memory Protection Unit
– Open Architecture with 3rd Party Support
• Operating Conditions
– Three CAN Controllers (DCAN)
•
•
64 mailboxes with parity protection each
Compliant to CAN protocol version 2.0B
– Up to 200MHz System Clock
– Inter-Integrated Circuit (I2C)
– Core Supply Voltage (VCC): 1.2V nominal
– I/O Supply Voltage (VCCIO): 3.3V nominal
• Integrated Memory
– Up to 3MB Program Flash with ECC
– Up to 256KB RAM with ECC
– 64KB Flash for emulated EEPROM
• 16- bit External Memory Interface
• Common Platform Architecture
– Three Multi-buffered Serial Peripheral
Interfaces (MibSPI)
•
128 Words with Parity Protection each
– Two Standard Serial Peripheral Interfaces
(SPI)
– Local Interconnect Network Interface (LIN)
Controller
•
Compliant to LIN protocol version 2.1
– Consistent memory map across family
– Real-Time Interrupt Timer (RTI) OS Timer
– 96-channel Vectored Interrupt Module (VIM)
– 2-channel Cyclic Redundancy Checker (CRC)
• Direct Memory Access (DMA) Controller
– 16 Channels and 32 Control Packets
– Parity protection for control packet RAM
– DMA Accesses Protected by Dedicated MPU
– Standard Serial Communication Interface
(SCI)
• Two High-End Timer Modules (N2HET)
– N2HET1: 32 programmable channels
– N2HET2: 20 programmable channels
– 160 Word Instruction RAM with parity
protection each
– Each includes Hardware Angle Generator
– Dedicated Transfer Unit for each N2HET
• Frequency-Modulated Phase-Locked-Loop
(HTU)
(FMPLL) with Built-In Slip Detector
• Two 10/12-bit Multi-Buffered ADC Modules
– ADC1: 24 channels
• Separate Non-Modulating PLL
• IEEE 1149.1 JTAG, Boundary Scan and ARM
CoreSight Components
– ADC2: 16 channels
• JTAG Security Module
– 16 shared channels
• Trace and Calibration Capabilities
– Embedded Trace Macrocell (ETM-R4)
– Data Modification Module (DMM)
– RAM Trace Port (RTP)
– 64 result buffers with parity protection each
• Packages
– 144-pin Quad Flatpack (PGE) [Green]
– 337-Ball Grid Array (ZWT) [Green]
– Parameter Overlay Module (POM)
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Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative
Copyright © 2011, Texas Instruments Incorporated
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
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