RM46L450
RM46L850
www.ti.com
SPNS184 –SEPTEMBER 2012
4.5.6.1 Application Sequence for CPU Self-Test
1. Configure clock domain frequencies.
2. Select number of test intervals to be run.
3. Configure the timeout period for the self-test run.
4. Enable self-test.
5. Wait for CPU reset.
6. In the reset handler, read CPU self-test status to identify any failures.
7. Retrieve CPU state if required.
For more information see the device Technical Reference Manual.
4.5.6.2 CPU Self-Test Clock Configuration
The maximum clock rate for the self-test is 100MHz. The STCCLK is divided down from the CPU clock.
This divider is configured by the STCCLKDIV register at address 0xFFFFE108.
For more information see the device Technical Reference Manual.
4.5.6.3 CPU Self-Test Coverage
Table 4-7 shows CPU test coverage achieved for each self-test interval. It also lists the cumulative test
cycles. The test time can be calculated by multiplying the number of test cycles with the STC clock period.
Table 4-7. CPU Self-Test Coverage
INTERVALS
TEST COVERAGE, %
0
TEST CYCLES
0
0
1
62.13
70.09
74.49
77.28
79.28
80.90
82.02
83.10
84.08
84.87
85.59
86.11
86.67
87.16
87.61
87.98
88.38
88.69
88.98
89.28
89.50
89.76
90.01
90.21
1365
2
2730
3
4095
4
5460
5
6825
6
8190
7
9555
8
10920
12285
13650
15015
16380
17745
19110
20475
21840
23205
24570
25935
27300
28665
30030
31395
32760
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Copyright © 2012, Texas Instruments Incorporated
System Information and Electrical Specifications
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