ADS1259
SBAS424C –JUNE 2009–REVISED MARCH 2010
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DIGITAL FILTER
The SINC2 register bit selects either the sinc1 or sinc2
filter. The sinc1 filter settles in one conversion cycle
while the sinc2 filter settles in two conversion cycles.
However, the sinc2 filter has the benefit of wider
frequency notches which improve line cycle rejection.
The programmable low-pass digital filter receives the
modulator output and produces a high-resolution
digital output. By adjusting the amount of filtering,
tradeoffs can be made between resolution and data
rate: filter more for higher resolution, filter less for
higher data rate.
FREQUENCY RESPONSE
The low-pass digital filter sets the overall frequency
response of the ADS1259. The filter response is the
product of the fixed and programmable filter sections,
and is given by Equation 4:
The filter consists of two sections: a fixed decimation
sinc5 filter followed by a variable decimation filter,
configurable as sinc1 or sinc2, as illustrated in
Figure 38. The sinc5 filter has fixed decimation of 64
and reduces the data rate of the modulator from
fCLK/8 to fCLK/512. The second filter stage receives the
data from the sinc5 filter. The second filter stage has
programmable averaging (or decimation) and can be
configured in either sinc1 or sinc2 mode. The
decimation ratio of this stage sets the final output
data rate. As detailed in Table 3, the DR[2:0] register
bits program the decimation ratio and the final output
data rate. The output data rates are identical for both
sinc1 and sinc2 filters.
½H(f)½ = ½Hsinc5(f)½ ´ ½HsincN(f)½ =
5
N
512p ´ f
512p ´ R ´ f
sin
sin
fCLK
fCLK
´
8p ´ f
512p ´ f
64 ´ sin
R ´ sin
fCLK
fCLK
where:
N = 1 (sinc1)
N = 2 (sinc2)
Table 3. Decimation Ratio of Final Filter Stage
R = Decimation ratio (refer to Table 3)
(4)
DR[2:0] REGISTER
BITS
DECIMATION
RATIO (R)
DATA RATE (SPS)
The digital filter attenuates noise on the modulator
output, including noise from within the ADS1259 and
external noise present within the ADS1259 input
signal. Adjusting the filtering by changing the
decimation ratio used in the programmable filter
changes the filter bandwidth. With a higher number of
decimation, the bandwidth is reduced and more noise
is attenuated.
111
110
101
100
011
010
001
000
1
4
14400
3600
1200
400
60
12
36
240
288
864
1440
50
16.6
10
Modulator Rate = fCLK/8
fCLK/512
sinc1 Filter
sinc5 Filter
(decimate by 64)
Output
Data Rate = fCLK/(R ´ 512)
Analog
Modulator
sinc2 Filter
SINC2 Register Bit
(0 = sinc1)
DR[2:0] Register Bits
(Program Decimation)
Figure 38. Block Diagram of Digital Filter
18
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