PCM9211
www.ti.com
SBAS495 –JUNE 2010
Register 6Bh, Main Output Port (SCKO/BCK/LRCK/DOUT) Source Setting
(Address: 6Bh, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
MOSSRC2
0
B5
MOSSRC1
0
B4
MOSSRC0
0
B3
RSV
0
B2
MOPSRC2
0
B1
B0
MOPSRC1
0
MOPSRC0
0
MOSSRC[2:0]: Main Output Port, SCK Source Control
000: DIR/ADC Automatic (DIR lock:DIR, DIR unlock:ADC) (default)
001: DIR
010: ADC
011: AUXIN0
100: AUXIN1
101: AUXIN2
110: Reserved
111: Reserved
MOPSRC[2:0]: Main Output Port, BCK/LRCK/DATA Source Control
000: DIR/ADC Automatic (DIR lock:DIR, DIR unlock:ADC) (default)
001: DIR
010: ADC
011: AUXIN0
100: AUXIN1
101: AUXIN2
110: Reserved
111: Reserved
This source control register is divided into two parts (MOSSRC and MOPSRC). This architecture allows some
additional functionality such as jitter cleaning. To clean the clock jitter of the HDMI receiver output, the HDMI
receiver S/PDIF output is connected with the PCM9211 S/PDIF input, and the HDMI receiver I2S outputs
(BCK/LRCK/DATA) are connected with the PCM9211 PCM input port.
Copyright © 2010, Texas Instruments Incorporated
Submit Documentation Feedback
97
Product Folder Link(s): PCM9211
TI [ TEXAS INSTRUMENTS ]
