PCM9211
SBAS495 –JUNE 2010
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Register 31h, XTI Source, Clock (SCK/BCK/LRCK) Frequency Setting
(Address: 31h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
XSCK1
0
B4
XSCK0
1
B3
XBCK1
1
B2
XBCK0
0
B1
XLRCK1
1
B0
XLRCK0
0
XSCK[1:0]: XTI Clock Source Frequency Setting
00: XTI/1 (24.576 MHz)
01: XTI/2 (12.288 MHz) (default)
10: XTI/4 (6.144 MHz)
11: XTI/8 (3.072 MHz)
XBCK[1:0]: XTI Clock Source BCK Frequency Setting
00: XTI/2 (12.288 MHz)
01: XTI/4 (6.144 MHz)
10: XTI/8 (3.072 MHz) (default)
11: XTI/16 (1.536 MHz)
XLRCK[1:0]: XTI Clock Source LRCK Frequency Setting
00: XTI/128 (192 kHz)
01: XTI/256 (96 kHz)
10: XTI/512 (48 kHz) (default)
11: XTI/1024 (24 kHz)
NOTE
The XTI clock source frequency is allowed to be set over the maximum limit of the ADC
allowable clock frequency. However, setting the XTI clock source frequency at such a
level is not recommended and may cause the device to exceed its stated operating and
performance limits.
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