PCM9211
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SBAS495 –JUNE 2010
Register 32h, DIR Source, Secondary Bit/LR Clock (SBCK/SLRCK) Frequency Setting
(Address: 32h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
PSBCK2
0
B5
PSBCK1
1
B4
PSBCK0
0
B3
RSV
0
B2
PSLRCK2
0
B1
PSLRCK1
1
B0
PSLRCK0
0
PSBCK[2:0]: DIR Clock Source, Secondary BCK (SBCK) Frequency Setting
000: 16fS (BCK/4)
001: 32fS (BCK/2)
010: 64fS (1x BCK) (default)
011: 128fS (2x BCK)
100: 256fS (4x BCK)
101: Reserved
110: Reserved
111: Reserved
PSLRCK[2:0]: DIR Clock Source, Secondary LRCK (SLRCK) Frequency Setting
000: fS/4 (LRCK/4)
001: fS/2 (LRCK/2)
010: fS (1x LRCK) (default)
011: 2fS (2x LRCK)
100: 4fS (4x LRCK)
101: Reserved
110: Reserved
111: Reserved
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