PCM9211
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SBAS495 –JUNE 2010
Register 30h, DIR Recovered System Clock (SCK) Ratio Setting
(Address: 30h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
RSV
0
B4
PSCKAUTO
0
B3
RSV
0
B2
PSCK2
0
B1
PSCK1
1
B0
PSCK0
0
PSCKAUTO: PLL SCK Dividing Ratio Automatic Control Setting
0: Disable (default)
1: Enable
This register is used to set the PLL SCK dividing ratio automatic control function.
SCK setting is automatically set depending on the input sampling frequency.
512fS: 54 kHz and below
256fS: 54 kHz to 108 kHz
128fS: 108 kHz and above or unlocked
The register setting of PSCKAUTO is prioritized higher than the PSCK[2:0] register setting.
For instance, if PSCKAUTO = '1', the PSCK[2:0] register setting is ignored.
To use this function, the XTI clock source is required.
PSCK[2:0]: DIR Recovered Clock Frequency Setting
000: 128fS
001: Reserved
010: 256fS (default)
011: Reserved
100: 512fS
101: Reserved
110: Reserved
111: Reserved
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