PCM9211
SBAS495 –JUNE 2010
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Typical Register Settings
Table 31 and Table 32 show the typical register settings for DSD format.
Table 31. DSD Inputs From MPIO_Cx Ports
REGISTER SETTINGS
34h = CFh
DESCRIPTIONS
RXSEL = TXOUT
TXDSD = Enable
61h = 14h
6Bh = 14h
MOSSRC = DIR
MOPSRC = AUXIN1
Table 32. DSD Inputs From MPIO_Bx Ports
REGISTER SETTINGS
34h = CFh
DESCRIPTIONS
RXSEL = TXOUT
60h = 55h
TXSSRC = AUXIN2
TXPSRC = AUXIN2
61h = 14h
6Bh = 14h
TXDSD = Enable
MOSSRC = DIR
MOPSRC = AUXIN1
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