PCM9211
www.ti.com
SBAS495 –JUNE 2010
Default Routing Function (After RESET)
The default routing paths are shown in Figure 32. MPIO_A0-A3 are selected by CLKST, VOUT, XMCKO, and
INT0. Note that by default, MPIO_A0-A3 pins are Hi-Z as set by Registers MPA0HZ, MPA1HZ, MPA2HZ, and
MPA3HZ.
FILT
AUXIN0
AUTO
RXIN7
DIR
RXIN0
RXIN0
DIR
SCKO
DOUT
RXIN1
RXIN1
RXIN2
RXIN3
RXIN4
RXIN5
RXIN6
RXIN7
ADC
BCK
LRCK
DOUT
MAIN
OUTPUT
PORT
PLL
AUXIN0
AUXIN1
AUXIN2
RXIN2
SCKO/BCK/LRCK
RXIN3
Lock:DIR
RXIN4/ASCKI0
RXIN5/ABCKI0
RXIN6/ALRCKI0
RXIN7/ADIN0
Unlock:ADC
Clock/Data
Recovery
AUTO
DIR
MPIO_A0(CLKST)
MPIO_A1(VOUT)
MPIO_A2(XMCKO)
MPIO_A3(INT0)
RXIN8
ADC
Lock Detection
DIT
RXIN9
AUXIN0
AUXIN1
AUXIN2
MPIO_A
RXIN10
RXIN11
DITOUT
SELECTOR
RECOUT0
RECOUT1
These pins are Hi-Z
at default.
RECOUT0
RECOUT1
DITOUT
MPO0(TXOUT)
MPO1(VOUT)
MPO0/1
SELECTOR
ADC
VINL
VINR
ADC Mode
Control
ADC
VCOM
Com. Supply
AUTO
DIR
MPIO _C0(TXSCK)
MPIO _C1(TXBCK)
MPIO _C2(TXLRCK)
MPIO _C3(TXDIN)
MPIO_B0(ASCKI2)
MPIO_B1(ABCKI2)
MPIO_B2(ALRCKI2)
MPIO_B3(ADIN2)
ADC Standalone
ADC
MPIO_C
AUXOUT
AUXIN2
MPIO _B
AUXIN0
AUXIN1
SELECTOR
SELECTOR
AUXIN1
ADC Clock
(SCK/BCK/LRCK)
Divider
XTI
XTO
OSC
XMCKO
(To MPIO _A & MPO0/1)
SBCK/SLRCK
Secondary BCK/LRCK
Divider
(to MPIO_A)
XMCKO
Divider
Selector
EXTRA DIR FUNCTIONS
REGISTER
ERROR/INT0(ERROR )
NPCM/INT1(NPCM )
DIR
PC and PD
DIR
fS Calculator
Function
Control
DIR CS
(48-bit)
ERROR DETECTION
Non-PCM DETECTION
fS Calculator
MPIO_A
MPIO_B
MPIO_C
MPO0
All Port
fS Calculator
GPIO/GPO
Data
DIT CS
(48-bit)
Flags
DIR Interrupt
DTS-CD/LD Detection
Validity Flag
User Data
Channel Status Data
BFRAME Detection
Interrupt System
MPO1
Figure 32. Default Routing Block Diagram
By default, the ADC starts up as a clock slave to the crystal that is connected to the PCM9211. The DIR receives
data on RXIN2. When the DIR is unlocked, the ADC has priority, and uses the Main port. When the DIR is
locked, data from the MAIN PORT are DIR data.
Copyright © 2010, Texas Instruments Incorporated
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