PCM9211
SBAS495 –JUNE 2010
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Register 70h, MPIO_A Flags or GPIO Assign Setting
(Address: 70h, Write and Read)
DATA
Reg Name
Default Value
Memo
B7
RSV
0
B6
RSV
0
B5
B4
B3
MPA3SEL
0
B2
MPA2SEL
0
B1
MPA1SEL
0
B0
MPA0SEL
0
MCHRSRC1 MCHRSRC0
0
0
MCHRSRC: AUX Output Port, SCK Source Control
00: See Table 29, Multi-Channel PCM Routing (default)
01: See Table 29, Multi-Channel PCM Routing
10: See Table 29, Multi-Channel PCM Routing
11: See Table 29, Multi-Channel PCM Routing
MPA3SEL: MPIO_A3 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPA3FLG[3:0] (default)
1: GPIO, set by GIOA3DIR/GPOA3/GPIA3
MPA2SEL: MPIO_A2 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPA2FLG[3:0] (default)
1: GPIO, set by GIOA2DIR/GPOA2/GPIA2
MPA1SEL: MPIO_A1 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPA1FLG[3:0] (default)
1: GPIO, set by GIOA1DIR/GPOA1/GPIA1
MPA0SEL: MPIO_A0 Pin Function, DIR Flags or GPIO Select
0: DIR Flags, set by MPA0FLG[3:0] (default)
1: GPIO, set by GIOA0DIR/GPOA0/GPIA0
102
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