8.18 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the SD host controller related to PCI power
management. See Table 8−13 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management capabilities
RU
0
R
1
R
1
R
1
R
1
R
1
R
1
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R
0
Register:
Offset:
Type:
Power management capabilities
82h
Read/Update, Read-only
7E02h
Default:
Table 8−13. Power Management Capabilities Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
15
PME_D3COLD
RU
PME support from D3
. This bit can be set to 1 or cleared to 0 via bit 4 (D3_COLD) in the general
cold
control register at offset 88h in the PCI configuration space (see Section 8.22). When this bit is set to
1, it indicates that the SD host controller is capable of generating a PME wake event from D3 . This
cold
implementation and may be configured by
bit state is dependent upon the SD host controller V
using bit 4 (D3_COLD) in the general control register (see Section 8.22).
AUX
14−11
PME_SUPPORT
R
PME support. This 4-bit field indicates the power states from which the SD host controller may assert
PME. This field returns a value of 1111b by default, indicating that PME may be asserted from
the D3 , D2, D1, and D0 power states.
hot
10
9
D2_SUPPORT
D1_SUPPORT
AUX_CURRENT
DSI
R
R
R
R
D2 support. Bit 10 is hardwired to 1, indicating that the SD host controller supports the D2 power state.
D1 support. Bit 9 is hardwired to 1, indicating that the SD host controller supports the D1 power state.
8−6
5
3.3-V auxiliary current requirements. This requirement is design dependent.
AUX
Device-specific initialization. This bit returns 0 when read, indicating that the SD host controller does
not require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
4
3
RSVD
R
R
Reserved. Bit 4 returns 0 when read.
PME_CLK
PME clock. This bit returns 0 when read, indicating that the PCI clock is not required for the SD host
controller to generate PME.
2−0
PM_VERSION
R
Power-management version. This field returns 010b when read, indicating that the SD host controller
is compatible with the registers described in the PCI Bus Power Management Interface Specification
(Revision 1.1).
8−12
TI [ TEXAS INSTRUMENTS ]
