8.23 Subsystem Access Register
The contents of the subsystem access register are aliased to the subsystem vendor ID and subsystem ID registers
at PCI offsets 2Ch and 2Eh, respectively. See Table 8−16 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Subsystem access
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Subsystem access
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
Register:
Offset:
Type:
Subsystem access
8Ch
Read/Write
0000 0000h
Default:
Table 8−16. Subsystem Access Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31−16
SubsystemID
RW
Subsystem device ID. The value written to this field is aliased to the subsystem ID register at
PCI offset 2Eh.
15−0
SubsystemVendorID
RW
Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 2Ch.
8.24 Diagnostic Register
This register enables the diagnostic modes. See Table 8−17 for a complete description of the register contents. All
bits in this register are reset by GRST only.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Diagnostic
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
RW
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Diagnostic
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Type:
Offset:
Default:
Diagnostic
Read-only, Read/Write
90h
0000 0000h
Table 8−17. Diagnostic Register Description
BIT
31−17
16
SIGNAL
RSVD
TYPE
R
FUNCTION
Reserved. Bits 31−17 return 0s when read.
DIAGNOSTIC
RSVD
RW
R
Diagnostic test bit. This test bit shortens the card detect debounce times for simulation and TDL.
Reserved. Bits 15−0 return 0s when read.
15−0
8−15
TI [ TEXAS INSTRUMENTS ]
