8.15 Maximum Latency Register
The maximum latency register contains the maximum latency value for the SD host controller core.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Maximum latency
RU
0
RU
0
RU
0
RU
0
RU
0
RU
1
RU
0
RU
0
Register:
Offset:
Type:
Maximum latency
3Fh
Read/Update
04h
Default:
Table 8−10. Maximum Latency Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
7−0
MAX_LAT
RU
Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level
to the SD host controller. The default for this register indicates that the SD host controller may need to
access the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The
contents of this field may also be loaded through the serial EEPROM.
8.16 Slot Information Register
This read-only register contains information on the number of SD sockets implemented and the base address
Registers used.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Slot information
R
0
R
X
R
X
R
X
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Maximum latency
40h
Read/Update
X0h
Default:
Table 8−11. Maximum Latency Register Description
BIT
7
FIELD NAME
RSVD
TYPE
DESCRIPTION
R
R
Reserved. This bit returns 0 when read.
6−4
NUMBER_SLOTS
Number of slots. This field indicates the number of SD sockets supported by the SD host controller.
Since the controller supports three SD sockets, this field returns 010 when read.
3
RSVD
R
R
Reserved. This bit returns 0 when read.
2−0
FIRST_BAR
First base address register number. This field is hardwired to 000b to indicate that the first BAR used
for the SD host standard registers is BAR0.
8−10
TI [ TEXAS INSTRUMENTS ]
