8.5 Class Code and Revision ID Register
The class code and revision ID register categorizes the base class, subclass, and programming interface of the
function. The base class is 08h, identifying the controller as a generic system peripheral. The subclass is 05h,
identifying the function as an SD host controller. The programming interface is 01h, indicating that the function is a
standard SD host with DMA capabilities. Furthermore, the TI chip revision is indicated in the least significant byte
(00h). See Table 8−4 for a complete description of the register contents.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Class code and revision ID
R
0
R
0
R
0
R
0
R
1
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
1
2
R
0
1
R
1
0
15
14
13
12
11
10
Name
Type
Default
Class code and revision ID
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
Register:
Offset:
Type:
Class code and revision ID
08h
Read-only
0805 0XXXh
Default:
Table 8−4. Class Code and Revision ID Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31−24
BASECLASS
R
Base class. This field returns 08h when read, which broadly classifies the function as a generic system
peripheral.
23−16
15−8
SUBCLASS
PGMIF
R
R
Subclass. This field returns 05h when read, which specifically classifies the function as an SD host
controller.
Programming interface. If bit 0 (DMA_EN) in the general control register is 0, then this field returns 00h
when read to indicate that the function is a standard SD host without DMA capabilities. If the DMA_EN
bit is 1, then this field returns 01h when read to indicate that the function is a standard SD host with
DMA capabilities.
7−0
CHIPREV
R
Silicon revision. This field returns the silicon revision of the SD host controller.
8−5
TI [ TEXAS INSTRUMENTS ]
