8.3 Command Register
The command register provides control over the SD host controller interface to the PCI bus. All bit functions adhere
to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 8−2 for a
complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Command
R
0
R
0
R
0
R
0
R
0
RW
0
R
0
RW
0
R
0
RW
0
R
0
RW
0
R
0
RW
0
RW
0
R
0
Register:
Offset:
Type:
Command
04h
Read/Write, Read-only
0000h
Default:
Table 8−2. Command Register Description
BIT
15−11
10
FIELD NAME
RSVD
TYPE
R
DESCRIPTION
Reserved. Bits 15−11 return 0s when read.
INT_DISABLE
RW
INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx assertion is enabled (default)
1 = INTx assertion is disabled
9
8
7
6
5
4
3
2
1
0
FBB_ENB
SERR_ENB
STEP_ENB
PERR_ENB
VGA_ENB
R
RW
R
Fast back-to-back enable. The SD host controller does not generate fast back-to-back transactions;
therefore, bit 9 returns 0 when read.
SERR enable. When bit 8 is set to 1, the SD host controller SERR driver is enabled. SERR can be
asserted after detecting an address parity error on the PCI bus.
Address/data stepping control. The SD host controller does not support address/data stepping;
therefore, bit 7 is hardwired to 0.
RW
R
Parity error enable. When bit 6 is set to 1, the SD host controller is enabled to drive PERR response
to parity errors through the PERR signal.
VGA palette snoop enable. The SD host controller does not feature VGA palette snooping; therefore,
bit 5 returns 0 when read.
MWI_ENB
RW
R
Memory write and invalidate enable. The SD host controller does not generate memory write invalidate
transactions; therefore, bit 4 returns 0 when read.
SPECIAL
Special cycle enable. The SD host controller does not respond to special cycle transactions; therefore,
bit 3 returns 0 when read.
MASTER_ENB
MEMORY_ENB
IO_ENB
RW
RW
R
Bus master enable. When bit 2 is set to 1, the SD host controller is enabled to initiate cycles on the
PCI bus.
Memory response enable. Setting bit 1 to 1 enables the SD host controller to respond to memory cycles
on the PCI bus.
I/O space enable. The SD host controller does not implement any I/O-mapped functionality; therefore,
bit 0 returns 0 when read.
8−3
TI [ TEXAS INSTRUMENTS ]
