8 SD Host Controller Programming Model
This section describes the internal PCI configuration registers used to program the PCI6x21/PCI6x11 SD host
controller interface. All registers are detailed in the same format: a brief description for each register is followed by
the register offset and a bit table describing the reset state for each register.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1
describes the field access tags.
The PCI6x21/PCI6x11 controller is a multifunction PCI device. The SD host controller core is integrated as PCI
function 4. The function 4 configuration header is compliant with the PCI Local Bus Specification as a standard
header. Table 8−1 illustrates the configuration header that includes both the predefined portion of the configuration
space and the user-definable registers.
Table 8−1. Function 4 Configuration Register Map
REGISTER NAME
OFFSET
00h
Device ID
Status
Vendor ID
Command
04h
Class code
Header type
Slot 0 base address
Revision ID
Cache line size
08h
BIST
Latency timer
0Ch
10h
Slot 1 base address
Slot 2 base address
Reserved
14h
18h
1Ch−28h
2Ch
Subsystem ID ‡
Subsystem vendor ID ‡
Reserved
30h
PCI power
management
Reserved
34h
capabilities pointer
Reserved
Minimum grant Interrupt pin
Reserved
38h
3Ch
Maximum latency
Interrupt line
Slot information
40h
Reserved
Next item pointer
44h−7Ch
80h
Power management capabilities
Capability ID
PM data
PMCSR_BSE
(Reserved)
Power management control and status ‡
General control ‡
84h
Reserved
88h
8Ch
90h
Subsystem alias
Diagnostic ‡
Slot 0 3.3-V
maximum current
Reserved
Reserved
Reserved
94h
98h
Slot 1 3.3-V
maximum current
Slot 2 3.3-V
maximum current
9Ch
Reserved
One or more bits in this register are cleared only by the assertion of GRST.
A0h−FCh
‡
8−1
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