7.23 Diagnostic Register
This register programs the M and N inputs to the PLL and enables the diagnostic modes. The default values for M
and N in this register set the PLL output to be 80 MHz, which is divided to get the 40 MHz and 20 MHz needed by
the flash media cores. See Table 7−16 for a complete description of the register contents. All bits in this register are
reset by GRST only.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Name
Type
Default
Bit
Diagnostic
R
0
R
0
R
0
R
0
R
0
R
0
R
0
9
R
0
8
R
0
7
R
0
6
R
0
5
R
0
4
R
0
3
R
0
2
R
0
1
R/W
0
15
14
13
12
11
10
0
Name
Type
Default
Diagnostic
R
0
R
0
R
0
R
0
R
0
R
0
R
1
R/W
1
R
0
R
0
R
0
RW
0
RW
0
RW
1
RW
0
RW
1
Register:
Type:
Offset:
Default:
Diagnostic
Read-only, Read/Write
54h
0000 0305h
Table 7−16. Diagnostic Register Description
BIT
SIGNAL
TYPE
FUNCTION
31−17
TBD_CTRL
R
PLL control bits. These bits are reserved for PLL control and test bits.
Diagnostic test bit. This test bit shortens the PLL clock CLK_VALID time and shortens the card detect
debounce times for simulation and TDL.
16
DIAGNOSTIC
RW
15−11
10−8
7−5
RSVD
PLL_N
RSVD
PLL_M
R
RW
R
Reserved. Bits 15−11 return 0s when read.
PLL_N input. The default value of this field is 03h.
Reserved. Bits 7−5 return 0s when read.
4−0
RW
PLL_M input. The default value of this field is 05h.
7−15
TI [ TEXAS INSTRUMENTS ]
