7.18 Power Management Control and Status Register
The power management control and status register implements the control and status of the flash media controller.
This register is not affected by the internally generated reset caused by the transition from the D3 to D0 state. See
hot
Table 7−13 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management control and status
RCU
0
R
0
R
0
R
0
R
0
R
0
R
0
RW
0
R
0
R
0
R
0
R
0
R
0
R
0
RW
0
RW
0
Register:
Offset:
Type:
Power management control and status
48h
Read/Clear, Read/Write, Read-only
0000h
Default:
Table 7−13. Power Management Control and Status Register Description
BIT
15 ‡
14−13
12−9
8 ‡
FIELD NAME
PME_STAT
DATA_SCALE
DATA_SELECT
PME_EN
TYPE
RCU
R
DESCRIPTION
PME status. This bit defaults to 0.
This field returns 0s, because the data register is not implemented.
This field returns 0s, because the data register is not implemented.
PME enable. Enables PME signaling. assertion is disabled.
Reserved. Bits 7−2 return 0s when read.
R
RW
R
7−2
RSVD
1−0 ‡
PWR_STATE
RW
Power state. This 2-bit field determines the current power state and sets the flash media controller to
a new power state. This field is encoded as follows:
00 = Current power state is D0.
01 = Current power state is D1.
10 = Current power state is D2.
11 = Current power state is D3
.
hot
‡
One or more bits in this register are cleared only by the assertion of GRST.
7.19 Power Management Bridge Support Extension Register
The power management bridge support extension register provides extended power-management features not
applicable to the flash media controller; thus, it is read-only and returns 0 when read.
Bit
7
6
5
4
3
2
1
0
Name
Type
Default
Power management bridge support extension
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
Register:
Offset:
Type:
Power management bridge support extension
4Ah
Read-only
00h
Default:
7−12
TI [ TEXAS INSTRUMENTS ]
