4.43 Power Management Capabilities Register
The power management capabilities register contains information on the capabilities of the PC Card function related
to power management. Both PCI6x21/PCI6x11 CardBus bridge functions support D0, D1, D2, and D3 power states.
Default register value is FE12h for operation in accordance with PCI Bus Power Management Interface Specification
revision 1.1. See Table 4−19 for a complete description of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
Type
Default
Power management capabilities
RW
1
R
1
R
1
R
1
R
1
R
1
R
1
R
0
R
0
R
0
R
0
R
1
R
0
R
0
R
1
R
0
Register:
Offset:
Type:
Power management capabilities
A2h (Functions 0, 1)
Read-only, Read/Write
FE12h
Default:
Table 4−19. Power Management Capabilities Register Description
BIT
SIGNAL
TYPE
FUNCTION
This 5-bit field indicates the power states from which the PCI6x21/PCI6x11 controller functions can assert
PME. A 0 for any bit indicates that the function cannot assert the PME signal while in that power state.
These 5 bits return 11111b when read. Each of these bits is described below:
15 ‡
RW
R
Bit 15 − defaults to a 1 indicating the PME signal can be asserted from the D3
because wake-up support from D3
cold
state. This bit is read/write
is contingent on the system providing an auxiliary power source
cold
to the V
terminals for D3
cold
terminals. If the system designer chooses not to provide an auxiliary power source to the V
PME support
CC
CC
wake-up support, then BIOS must write a 0 to this bit.
14−11
Bit 14 − contains the value 1 to indicate that the PME signal can be asserted from the D3 state.
hot
Bit 13 − contains the value 1 to indicate that the PME signal can be asserted from the D2 state.
Bit 12 − contains the value 1 to indicate that the PME signal can be asserted from the D1 state.
Bit 11 − contains the value 1 to indicate that the PME signal can be asserted from the D0 state.
10
9
D2_Support
D1_Support
RSVD
R
R
R
R
This bit returns a 1 when read, indicating that the function supports the D2 device power state.
This bit returns a 1 when read, indicating that the function supports the D1 device power state.
Reserved. These bits return 000b when read.
8−6
5
DSI
Device-specific initialization. This bit returns 0 when read.
Auxiliary power source. This bit is meaningful only if bit 15 (D3
supporting PME) is set. When this bit
cold
requires auxiliary power supplied by the system by way
is set, it indicates that support for PME in D3
of a proprietary delivery vehicle.
cold
4
AUX_PWR
R
A 0 (zero) in this bit field indicates that the function supplies its own auxiliary power source.
If the function does not support PME while in the D3
0.
state (bit 15=0), then this field must always return
cold
When this bit is 1, it indicates that the function relies on the presence of the PCI clock for PME operation.
When this bit is 0, it indicates that no PCI clock is required for the function to generate PME.
3
PMECLK
Version
R
R
Functions that do not support PME generation in any state must return 0 for this field.
These 3 bits return 010b when read, indicating that there are 4 bytes of general-purpose power
management (PM) registers as described in draft revision 1.1 of the PCI Bus Power Management Interface
Specification.
2−0
‡
One or more bits in this register are cleared only by the assertion of GRST.
4−31
TI [ TEXAS INSTRUMENTS ]
