OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Table 6-84. I2C Input Timing Requirements (continued)
NO.
MIN
20 + 0.1Cb
20 + 0.1Cb
20 + 0.1Cb
MAX UNIT
Standard Mode
Fast Mode
1000
ns
9
tr(SDA)
Rise time, I2Cx_SDA
Rise time, I2Cx_SCL
Fall time, I2Cx_SDA
Fall time, I2Cx_SCL
300
Standard Mode
Fast Mode
1000
ns
10
11
12
13
14
15
tr(SCL)
300
Standard Mode
Fast Mode
300
ns
tf(SDA)
300
Standard Mode
Fast Mode
300
ns
tf(SCL)
20 + 0.1Cb
300
Standard Mode
Fast Mode
4
0.6
N/A
0
Setup time, I2Cx_SCL high before I2Cx_SDA
high
tsu(SCLH-SDAH)
µs
Standard Mode
Fast Mode
tw(SP)
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
ns
50
Standard Mode
Fast Mode
400
pF
Cb
400
Table 6-85. I2C Switching Characteristics(1)
NO.
PARAMETER
MIN
10
2.5
4.7
0.6
4
MAX UNIT
Standard Mode
16
tc(SCL)
Cycle time, I2Cx_SCL
µs
Fast Mode
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
low
17
18
19
20
21
22
23
28
tsu(SCLH-SDAL)
th(SDAL-SCLL)
tw(SCLL)
µs
µs
µs
µs
ns
Standard Mode
Fast Mode
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
0.6
4.7
1.3
4
Standard Mode
Fast Mode
Standard Mode
Fast Mode
tw(SCLH)
Pulse duration, I2Cx_SCL high
0.6
250
100
0
Standard Mode
Fast Mode
Setup time, I2Cx_SDA valid before I2Cx_SCL
high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
tw(SDAH)
Standard Mode
Fast Mode
Hold time, I2Cx_SDA valid after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
µs
0
0.9
Standard Mode
Fast Mode
4.7
1.3
4
µs
µs
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
high
tsu(SCLH-SDAH)
0.6
(1) I2C must be configured correctly to meet the timings in Table 6-85.
192
Peripheral Information and Electrical Specifications
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