OMAP-L137 Low-Power Applications Processor
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SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
Table 6-83. Inter-Integrated Circuit (I2C) Registers
I2C0
I2C1
Acronym
Register Description
BYTE ADDRESS
0x01C2 2000
0x01C2 2004
0x01C2 2008
0x01C2 200C
0x01C2 2010
0x01C2 2014
0x01C2 2018
0x01C2 201C
0x01C2 2020
0x01C2 2024
0x01C2 2028
0x01C2 202C
0x01C2 2030
0x01C2 2034
0x01C2 2038
0x01C2 2048
0x01C2 204C
0x01C2 2050
0x01C2 2054
0x01C2 2058
0x01C2 205C
BYTE ADDRESS
0x01E2 8000
0x01E2 8004
0x01E2 8008
0x01E2 800C
0x01E2 8010
0x01E2 8014
0x01E2 8018
0x01E2 801C
0x01E2 8020
0x01E2 8024
0x01E2 8028
0x01E2 802C
0x01E2 8030
0x01E2 8034
0x01E2 8038
0x01E2 8048
0x01E2 804C
0x01E2 8050
0x01E2 8054
0x01E2 8058
0x01E2 805C
ICOAR
I2C Own Address Register
I2C Interrupt Mask Register
I2C Interrupt Status Register
I2C Clock Low-Time Divider Register
I2C Clock High-Time Divider Register
I2C Data Count Register
ICIMR
ICSTR
ICCLKL
ICCLKH
ICCNT
ICDRR
I2C Data Receive Register
I2C Slave Address Register
I2C Data Transmit Register
I2C Mode Register
ICSAR
ICDXR
ICMDR
ICIVR
I2C Interrupt Vector Register
I2C Extended Mode Register
I2C Prescaler Register
ICEMDR
ICPSC
REVID1
REVID2
ICPFUNC
ICPDIR
ICPDIN
ICPDOUT
ICPDSET
ICPDCLR
I2C Revision Identification Register 1
I2C Revision Identification Register 2
I2C Pin Function Register
I2C Pin Direction Register
I2C Pin Data In Register
I2C Pin Data Out Register
I2C Pin Data Set Register
I2C Pin Data Clear Register
6.24.3 I2C Electrical Data/Timing
6.24.3.1 Inter-Integrated Circuit (I2C) Timing
Table 6-84 and Table 6-85 assume testing over recommended operating conditions (see Figure 6-62 and
Figure 6-63).
Table 6-84. I2C Input Timing Requirements
NO.
MIN
10
MAX UNIT
Standard Mode
Fast Mode
1
tc(SCL)
Cycle time, I2Cx_SCL
µs
2.5
4.7
0.6
4
Standard Mode
Fast Mode
Setup time, I2Cx_SCL high before I2Cx_SDA
low
2
3
4
5
6
7
8
tsu(SCLH-SDAL)
th(SCLL-SDAL)
tw(SCLL)
µs
µs
µs
µs
ns
Standard Mode
Fast Mode
Hold time, I2Cx_SCL low after I2Cx_SDA low
Pulse duration, I2Cx_SCL low
0.6
4.7
1.3
4
Standard Mode
Fast Mode
Standard Mode
Fast Mode
tw(SCLH)
Pulse duration, I2Cx_SCL high
0.6
250
100
0
Standard Mode
Fast Mode
tsu(SDA-SCLH)
th(SDA-SCLL)
tw(SDAH)
Setup time, I2Cx_SDA before I2Cx_SCL high
Hold time, I2Cx_SDA after I2Cx_SCL low
Pulse duration, I2Cx_SDA high
Standard Mode
Fast Mode
µs
0
0.9
Standard Mode
Fast Mode
4.7
1.3
µs
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