OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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Table 6-45. McASP1 Switching Characteristics(1)
NO.
PARAMETER
MIN
20
MAX
UNIT
Cycle time, AHCLKX1 internal, AHCLKR1 output
Cycle time, AHCLKR1 external, AHCLKR1 output
Cycle time, AHCLKX1 internal, AHCLKX1 output
Cycle time, AHCLKX1 external, AHCLKX1 output
20
9
tc(AHCLKRX)
ns
20
20
Pulse duration, AHCLKR1 internal, AHCLKR1
output
(AHR/2) – 2.5(2)
(AHR/2) – 2.5(2)
(AHX/2) – 2.5(3)
(AHX/2) – 2.5(3)
Pulse duration, AHCLKR1 external, AHCLKR1
output
10
tw(AHCLKRX)
ns
Pulse duration, AHCLKX1 internal, AHCLKX1
output
Pulse duration, AHCLKX1 external, AHCLKX1
output
Cycle time, ACLKR1 internal, ACLKR1 output
Cycle time, ACLKR1 external, ACLKR1 output
Cycle time, ACLKX1 internal, ACLKX1 output
Cycle time, ACLKX1 external, ACLKX1 output
Pulse duration, ACLKR1 internal, ACLKR1 output
Pulse duration, ACLKR1 external, ACLKR1 output
Pulse duration, ACLKX1 internal, ACLKX1 output
Pulse duration, ACLKX1 external, ACLKX1 output
Delay time, ACLKR1 internal, AFSR output(7)
Delay time, ACLKX1 internal, AFSR output(8)
Delay time, ACLKX1 internal, AFSX output
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
greater of 2P or 20 ns(4)
11
12
tc(ACLKRX)
ns
ns
(AR/2) – 2.5(5)
(AR/2) – 2.5(5)
(AX/2) – 2.5(6)
(AX/2) – 2.5(6)
tw(ACLKRX)
0.5
0.5
0.5
3.9
3.9
3.9
6.7
6.7
6.7
Delay time, ACLKR1 external input, AFSR output(7)
Delay time, ACLKX1 external input, AFSR output(8)
Delay time, ACLKX1 external input, AFSX output
13.8
13.8
13.8
13
td(ACLKRX-AFSRX)
ns
Delay time, ACLKR1 external output, AFSR
output(7)
3.9
3.9
13.8
13.8
Delay time, ACLKX1 external output, AFSR
output(8)
Delay time, ACLKX1 external output, AFSX output
Delay time, ACLKX1 internal, AXR1[n] output
Delay time, ACLKX1 external input, AXR1[n] output
3.9
0.5
3.9
13.8
6.7
13.8
14
15
td(ACLKX-AXRV)
ns
ns
Delay time, ACLKX1 external output, AXR1[n]
output
3.9
0.5
3.9
13.8
6.7
Disable time, ACLKX1 internal, AXR1[n] output
Disable time, ACLKX1 external input, AXR1[n]
output
13.8
tdis(ACLKX-AXRHZ)
Disable time, ACLKX1 external output, AXR1[n]
output
3.9
13.8
(1) McASP1 ACLKX1 internal – ACLKXCTL.CLKXM = 1, PDIR.ACLKX = 1
McASP1 ACLKX1 external input – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 0
McASP1 ACLKX1 external output – ACLKXCTL.CLKXM = 0, PDIR.ACLKX = 1
McASP1 ACLKR1 internal – ACLKR1CTL.CLKRM = 1, PDIR.ACLKR =1
McASP1 ACLKR1 external input – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 0
McASP1 ACLKR1 external output – ACLKRCTL.CLKRM = 0, PDIR.ACLKR = 1
(2) AHR - Cycle time, AHCLKR1.
(3) AHX - Cycle time, AHCLKX1.
(4) P = SYSCLK2 period
(5) AR - ACLKR1 period.
(6) AX - ACLKX1 period.
(7) McASP1 ACLKXCTL.ASYNC=1: Receiver is clocked by its own ACLKR1
(8) McASP1 ACLKXCTL.ASYNC=0: Receiver is clocked by transmitter's ACLKX1
140
Peripheral Information and Electrical Specifications
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