OMAP-L137 Low-Power Applications Processor
SPRS563A–SEPTEMBER 2008–REVISED OCTOBER 2008
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EMA_A[1]
EMA_A[2]
EMA_D[7:0]
EMA_CS[2]
EMA_CS[3]
EMA_WE
ALE
CLE
DQ[7:0]
CE1
CE2
WE
NAND
FLASH
x8,
MultiPlane
EMA_OE
EMIFA
RE
R/B1
R/B2
EMA_WAIT
DVDD
ALE
CLE
DQ[7:0]
CE1
CE2
WE
NAND
FLASH
x8,
EMA_CS[4]
EMA_CS[5]
MultiPlane
RE
R/B1
R/B2
Figure 6-12. OMAP-L137 EMIFA Connection Diagram: Multiple NAND Flash Planes
6.10.4 External Memory Interface (EMIF)
Table 6-17 is a list of the EMIF registers. For more information about these registers, see the C674x DSP
External Memory Interface (EMIF) User's Guide (literature number SPRU711).
Table 6-17. External Memory Interface (EMIFA) Registers
BYTE ADDRESS
0x6800 0000
0x6800 0004
0x6800 0008
0x6800 000C
0x6800 0010
0x6800 0014
0x6800 0018
0x6800 001C
0x6800 0020
0x6800 003C
0x6800 0040
0x6800 0044
0x6800 0048
0x6800 004C
0x6800 0060
0x6800 0064
0x6800 0070
0x6800 0074
0x6800 0078
0x6800 007C
0x6800 00BC
0x6800 00C0
0x6800 00C4
Register Name
MIDR
Register Description
Module ID Register
AWCC
Asynchronous Wait Cycle Configuration Register
SDRAM Configuration Register
SDCR
SDRCR
SDRAM Refresh Control Register
Asynchronous 1 Configuration Register
Asynchronous 2 Configuration Register
Asynchronous 3 Configuration Register
Asynchronous 4 Configuration Register
SDRAM Timing Register
CE2CFG
CE3CFG
CE4CFG
CE5CFG
SDTIMR
SDSRETR
INTRAW
SDRAM Self Refresh Exit Timing Register
EMIFA Interrupt Raw Register
INTMSK
EMIFA Interrupt Mask Register
INTMSKSET
INTMSKCLR
NANDFCR
NANDFSR
NANDF1ECC
NANDF2ECC
NANDF3ECC
NANDF4ECC
NAND4BITECCLOAD
NAND4BITECC1
NAND4BITECC2
EMIFA Interrupt Mask Set Register
EMIFA Interrupt Mask Clear Register
NAND Flash Control Register
NAND Flash Status Register
NAND Flash 1 ECC Register (CS2 Space)
NAND Flash 2 ECC Register (CS3 Space)
NAND Flash 3 ECC Register (CS4 Space)
NAND Flash 4 ECC Register (CS5 Space)
NAND Flash 4-Bit ECC Load Register
NAND Flash 4-Bit ECC Register 1
NAND Flash 4-Bit ECC Register 2
106
Peripheral Information and Electrical Specifications
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