XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
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Table 4-34. Bit Descriptions – Global Chip Control Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Minimum power scale. This value is programmed to indicate the scale of the Minimum
Power Value field.
00 – 1.0x
MIN_POWER_SCA
LE
01 – 0.1x
21:20
rw
10 – 0.01x
11 – 0.001x
This field is loaded from EEPROM (when present) and reset with PERST.
Minimum power value. This value is programmed to indicate the minimum power
requirements for all circuitry powered by a slot, and is not applicable for motherboard
down applications (i.e., must be programmed to zero in that case). This value is multiplied
by the Minimum Power Scale field. When the value is non-zero, the resultant power figure
is compared against information conveyed in Set_Slot_Power_Limit Messages received
on the upstream port. When the value is zero, the comparison is ignored as if there is no
power limit.
MIN_POWER_VAL
UE
19:12
rw
This field is loaded from EEPROM (when present) and reset with PERST.
Power override. This field is used to determine how the device responds when the slot
power limit (via Set_Slot_Power_Limit Message received) is greater than the amount of
power programmed in the MIN_SLOT_POWER field of this register. This power
comparison is disabled when the MIN_SLOT_POWER field of the register is zero.
00 – Ignore slot power limit.
01 – Assert the PWR_OVER pin.
11:10
PWR_OVRD
rw
10 – Assert the PWR_OVER pin and respond with Unsupported request to all transactions
except configuration transactions (Type 0 or Type 1) and Set_Slot_Power_Limit
Messages.
11 – Reserved
This field is loaded from EEPROM (when present) and reset with PERST.
Reserved. When read, these bits return zeros.
9:3
2
RSVD
r
Wake or beacon. This bit controls whether wake events are signaled using the WAKE pin
or a beacon transmission.
0 – Beacon mode.
WAKE_OR_BCN
rwh
1 – WAKE mode.
This field is reset with GRST and is loaded from EEPROM (when present).
Wake to beacon enable. This bit enables externally generated wake events detected on
the WAKE pin to cause a beacon to be transmitted. This field is ignored if
WAKE_OR_BCN is set to WAKE mode.
1
0
WAKE2BCN
AUX_PRSNT
rwh
0 – WAKE input to beacon translation disabled.
1 – WAKE input to beacon translation enabled.
This field is reset with GRST and is loaded from EEPROM (when present).
AUX power present. This bit reflects the state of a 3.3-VAUX presence detection circuit
output in the PCI Express reference macro. This bit controls the AUX Power Detected bit
in the Device Status register (i.e., whether AUX power is present) for all ports.
ru
0 – AUX power is not present.
1 – AUX power is present.
4.2.61 GPIO A Control Register
This register is used to control the function of the PCIE_GPIO 0 – 4 pins.
PCI register offset:
Register type:
BCh
Read/Write; Read Only; Hardware Update; Sticky
0000h
Default value:
64
XIO3130 Configuration Register Space
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