欢迎访问ic37.com |
会员登录 免费注册
发布采购

NE5532PSE4 参数 Datasheet PDF下载

NE5532PSE4图片预览
型号: NE5532PSE4
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL OP-AMP, 5000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, PLASTIC, SO-8]
分类和应用: 放大器光电二极管
文件页数/大小: 142 页 / 1062 K
品牌: TI [ TEXAS INSTRUMENTS ]
 浏览型号NE5532PSE4的Datasheet PDF文件第61页浏览型号NE5532PSE4的Datasheet PDF文件第62页浏览型号NE5532PSE4的Datasheet PDF文件第63页浏览型号NE5532PSE4的Datasheet PDF文件第64页浏览型号NE5532PSE4的Datasheet PDF文件第66页浏览型号NE5532PSE4的Datasheet PDF文件第67页浏览型号NE5532PSE4的Datasheet PDF文件第68页浏览型号NE5532PSE4的Datasheet PDF文件第69页  
XIO3130  
www.ti.com  
SLLS693FMAY 2007REVISED JANUARY 2010  
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-35. Bit Descriptions – GPIO A Control Register  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
15  
RSVD  
r
Reserved. Reads back zero.  
GPIO 4 Control. This field controls the GPIO4 pin as follows:  
000 – General Purpose Input (default)  
001 – General Purpose Output  
010 – Port 1 ACT_BTN0  
011 – Port 3 ACT_BTN2  
100 – Port 1 PWRFLT0  
101 – Port 3 PWRFLT2  
14:12  
PCIE_GPIO4_CTL  
rw  
110 – Port 1 EMIL_ENG0  
111 – Port 3 EMIL_ENG2  
See GPIO Data register for a detailed description of this field.  
This field is loaded from EEPROM (if present), and reset with FRST.  
If the DN2_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO4 terminal  
is directly mapped as the PRESENT PCI Hot Plug terminal for port 3 and is no longer  
available for use as a GPIO. In this situation these bits have no meaning and should be left  
at their default value.  
GPIO 3 Control. This field controls the GPIO3 pin as follows:  
000 – General Purpose Input (default)  
001 – General Purpose Output  
010 – Port 1 CLKREQ0  
011 – Port 1 MRLS_DET0  
100 – Port 2 PWRFLT1  
11:9  
PCIE_GPIO3_CTL  
rw  
101 – Port 3 PWRFLT2  
110 – Port 2 MRLS_DET1  
111 – Port 3 MRLS_DET2,  
See GPIO Data register for a detailed description of this field.  
This field is loaded from EEPROM (if present), and reset with FRST.  
GPIO 2 Control. This field controls the GPIO2 pin as follows:  
000 – General Purpose Input (default)  
001 – General Purpose Output  
010 – Port 2 ACT_BTN1  
011 – Port 3 ACT_BTN2  
100 – Port 2 PWRFLT1  
101 – Port 3 PWRFLT2  
8:6  
PCIE_GPIO2_CTL  
rw  
110 – Port 2 MRLS_DET1  
111 – Port 3 MRLS_DET2  
See GPIO Data register for a detailed description of this field.  
This field is loaded from EEPROM (if present), and reset with FRST.  
If the DN1_DPSTRP terminal is pulled high at the de-assertion of reset, the GPIO2 terminal  
is directly mapped as the PWR_GOOD PCI Hot Plug terminal for port 2 and is no longer  
available for use as a GPIO. In this situation these bits have no meaning and should be left  
at their default value.  
Copyright © 2007–2010, Texas Instruments Incorporated  
XIO3130 Configuration Register Space  
65  
Submit Documentation Feedback  
Product Folder Link(s): XIO3130  
 复制成功!