XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-37. Bit Descriptions – GPIO C Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
15
RSVD
r
Reserved. Reads back zero.
GPIO 14 Control. This field controls the GPIO14 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_LED0
011 – Port 2 ACT_LED1
100 – Port 3 ACT_LED2
14:12
11:9
8:6
PCIE_GPIO14_CTL
PCIE_GPIO13_CTL
PCIE_GPIO12_CTL
PCIE_GPIO11_CTL
rw
rw
rw
rw
101 – Port 1 PWR_LED0
110 – Port 2 PWR_LED1
111 – Port 3 PWRFLT2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 12 Control. This field controls the GPIO12 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_LED0
011 – Port 2 ACT_LED1
100 – Port 3 ACT_LED2
101 – Port 1 ATN_LED0
110 – Port 2 PWR_LED1
111 – Port 3 PWR_LED2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 12 Control. This field controls the GPIO12 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 1 ACT_LED0
011 – Port 2 ACT_LED1
100 – Port 3 ACT_LED2
101 – Port 1 PWR_LED0
110 – Port 2 ATN_LED1
111 – Port 3 ATN_LED2
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
GPIO 11 Control. This field controls the GPIO11 pin as follows:
000 – General Purpose Input (default)
001 – General Purpose Output
010 – Port 3 CLKREQ2
011 – Port 3 MRLS_DET2
100 – Port 1 PWRFLT0
5:3
101 – Port 2 PWRFLT1
110 – Port 1 MRLS_DET0
111 – Port 2 MRLS_DET1,
See GPIO Data register for a detailed description of this field.
This field is loaded from EEPROM (if present), and reset with FRST.
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XIO3130 Configuration Register Space
69
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