XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
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Table 4-33. Bit Descriptions – Upstream Port Link PM Latency Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:14
RSVD
r
Endpoint L0s acceptable latency. This field is used to program the maximum acceptable
latency when exiting the L0s state. This field is used to set the L0s Acceptable Latency field in
the Device Capabilities register.
000 – Less than 64 ns (default)
001 – 64 ns up to less than 128 ns
010 – 128 ns up to less than 256 ns
011 – 256 ns up to less than 512 ns
100 – 512 ns up to less than 1 ms
101 – 1 ms up to less than 2 ms
13:11
EP_L0S_LAT
rw
110 – 2 ms to 4 ms
111 – More than 4 ms
This field is loaded from EEPROM (when present) and reset with PERST.
Endpoint L1 acceptable latency. This field is used to program the maximum acceptable latency
when exiting the L1 state. This field is used to set the L1 Acceptable Latency field in the Device
Capabilities register.
000 – Less than 1 ms (default)
001 – 1 ms up to less than 2 ms
010 – 2 ms up to less than 4 ms
10:8
EP_L1_LAT
rw
011 – 4 ms up to less than 8 ms
100 – 8 ms up to less than 16 ms
101 – 16 ms up to less than 32 ms
110 – 32 ms to 64 ms
111 – More than 64 ms
This field is loaded from EEPROM (when present) and reset with PERST.
Reserved. When read, these bits return zeros.
7:6
RSVD
r
L0s exit latency. This field is used to program the maximum latency for the PHY to exit the L0s
state. This field is used to set the L0s Exit Latency field in the Link Capabilities register.
000 – Less than 64 ns
001 – 64 ns up to less than 128 ns
010 – 128 ns up to less than 256 ns
011 – 256 ns up to less than 512 ns
100 – 512 ns up to less than 1 ms (default)
101 – 1 ms up to less than 2 ms
110 – 2 ms to 4 ms
5:3
L0S_EXIT_LAT
rw
111 – More than 4 ms
Define writtenBySW to default to false, be set to true whenever the software or serial EEPROM
writes this field to a value that is different from its current state, and can only be subsequently
set to false as a result of a reset. When writtenBySW is false, this field is set to 011b when the
CCC bit in the Link Control register is asserted (i.e., common clock mode) and set to 100b
when the CCC bit is de-asserted (i.e., non-common clock mode). When writtenBySW is true,
this field is the value that was last written by the software.
This field is loaded from EEPROM (when present) and reset with PERST.
This field may be programmed differently depending on the values programmed in the
DEFER_L_EXIT and SMART_L_EXIT fields in the Global Switch Control register.
62
XIO3130 Configuration Register Space
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