XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
5.2 PCI Hot Plug Timing
5.2.1 Power-Up Cycle
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The XIO3130 switch can be powered up numerous ways depending on the way the DPSTRP[2:0]
strapping defines the port. The different power-up cycles are: nonPCI Hot Plug power-up cycle, PCI Hot
Plug power-up cycle with PWRGDn feedback, and PCI Hot Plug power-up cycle without PWRGDn
feedback.
5.2.1.1 NonPCI Hot Plug Power-Up Cycle
For nonPCI Hot Plug power-up cycles, there are no PWRONn, PWRGDn, or PRSNTn signals, and the
Slot Control register is not used to power the port up. As soon as the REFCLKn output is stable on the
port, the PERSTn signal is de-asserted high. If no device is detected on the port before Link Training
times out, the PERSTn signal is asserted low and REFCLKn is disabled.
PERST#
PERSTn#
REFCLKn
Unstable
Stable
<100 ms
Figure 5-1. NonPCI Hot Plug Power-Up Cycle
5.2.1.2 PCI Hot Plug Power-Up Cycle With PWRGDn Feedback
For PCI Hot Plug power up cycles with PWRGDn feedback, the PWRONn signal going low gates the
power-up cycle. The XIO3130 switch asserts PWRONn and waits for the PWRGDn signal to transition
high, indicating that power to the slot is now stable. When PWRGDn goes high, REFCLKn is enabled and
a 100 ms time-out starts. After the 100 ms time-out completes, PERSTn is de-asserted. If the port has
been programmed (see GPIO Control Registers in sections Section 4.2.61 through Section 4.2.64) to have
a CLKREQn input when PERSTn de-asserts high, REFCLKn is disabled when CLKREQn is not low.
PWRONn#
PWRGDn
CLKREQn#
REFCLKn
PERSTn#
Unstable
Stable
>100 ms
100 ms
Figure 5-2. PCI Hot Plug Power-Up Cycle With PWFRDn Feedback
5.2.1.3 PCI Hot Plug Power-Up Cycle With No PWRGDn Feedback
This application requires the PWRGDn signal to be tied high. The PWRONn signal going low gates the
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PCI Hot Plug Implementation Overview
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