XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
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Table 4-89. Correctable Error Mask Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
Bad DLLP error mask.
7
BAD_DLLP_MASK
rwh
0 – Error condition is unmasked
1 – Error condition is masked
Bad TLP error mask.
6
5:1
0
BAD_TLP_MASK
RSVD
rwh
r
0 – Error condition is unmasked
1 – Error condition is masked
Reserved. Return zeros when read.
Receiver error mask.
RX_ERROR_MASK
rwh
0 – Error condition is unmasked
1 – Error condition is masked
4.3.71 Advanced Error Capabilities and Control Register
The Advanced Error Capabilities and Control register allows the system to monitor and control the
advanced error reporting capabilities.
PCI register offset:
Register type:
118h
Read Only, Read/Write
0000 00A0h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
Table 4-90. Advanced Error Capabilities and Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. Return zeros when read.
31:9
RSVD
r
Extended CRC check enable.
8
7
6
ECRC_CHK_EN
ECRC_CHK_CAPABLE
ECRC_GEN_EN
rwh
r
0 – Extended CRC checking is disabled
1 – Extended CRC checking is enabled
Extended CRC check capable. This read-only bit returns a value of ‘1’ indicating
that the bridge is capable of checking extended CRC information.
Extended CRC generation enable.
rwh
0 – Extended CRC generation is disabled
1 – Extended CRC generation is enabled
Extended CRC generation capable. This read-only bit returns a value of ‘1’
indicating that the bridge is capable of generating extended CRC information.
5
ECRC_GEN_CAPABLE
FIRST_ERR
r
First error pointer. This five-bit value reflects the bit position within the
Uncorrectable Error Status register corresponding to the class of the first error
condition that was detected.
4:0
rh
4.3.72 Header Log Register
The Header Log register stores the TLP header for the packet that lead to the most recently detected error
condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a
4DW TLP header).
PCI register offset:
11Ch – 128h
126
XIO3130 Configuration Register Space
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