XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 5-1. GPIO Matrix (continued)
GPIO[#]
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EMILENG3
7
7
In Table 2-11, S indicates a strapping option. If the appropriate DNn_DPSTRP pin is pulled high, the GPIO
is mapped to this value and is no longer mapped by the GPIO Control register.
Each downstream port of the XIO3130 is assigned one dedicated sideband pin, DNn_PERST. Three
additional sideband pins may be dedicated to each port for PCI Hot Plug support. The DNn_DPSTRP pins
are set for the corresponding ports to indicate support for PCI Hot Plug. When the DNn_DPSTRP pin
strapping defines a GPIO pin as a PCI Hot Plug support pin, that pin is associated with the Slot Capability,
Slot Status, and Slot Control registers of the corresponding downstream port. These registers are defined
in sections Section 4.3.55, Section 4.3.56, and Section 4.3.57, respectively. When the DPSTRP[2:0] pin
strapping defines a GPIO pin as a GPIO pin, that pin is mapped to a bit field in the GPIO Configuration
registers and Data register. These registers are defined in section Section 4.2.61 through Section 4.2.65.
Table 5-2. PCI Hot Plug Sideband Signals
Signal
I/O
Function
Dn_PERST
O
Port n PE Reset. The PCI Hot Plug card or device is held in a reset state when this signal is low.
Port n Present. A PCI Hot Plug card or device is attached to a port when this signal is low.
PRSNTn
I
This signal is reported in the PDC bit of the Slot Status register. When this signal is in a de-asserted high
state, the DNn_PERST pin is asserted low, REFCLK is disabled, and PWRONn is de-asserted high.
Port n Power On. Power is applied to the PCI Hot Plug card or device attached to the port when this
signal is low.
PWRONn
PWRGDn
O
I
Port n Power Good: The power to the PCI Hot Plug card or device is adequate and it is alright to enable
REFCLK to the card or device and de-assert DNn_PERST. When this signal transitions to a low state, the
XIO3130 switch asserts DNn_PERST low and turns off REFCLK.
Additional GPIO pins may be allocated to PCI Hot Plug support via programming by assigning the pins to
PCI Hot Plug pin functionality in the GPIO Control registers defined in sections Section 4.2.62 through
Section 4.2.65.
Table 5-3. Pins Assigned to GPIO Control Registers
Signal
CLKREQn
I/O
Function
Port n CLK REQ. This signal is used to disable the clock during normal operation. If PWRONn is high or
PRSNTn is high or PWRGDn is low, this signal is ignored by the XIO3130.
I
Port n Activity. This pin toggles at anytime activity is detected on the port interface. Otherwise, this pin is
high.
ACT_LEDn
O
PWR_LEDn
ATN_LEDn
ATN_BTNn
O
O
I
Port n Power Indicator: See PI_CTL bit field in Slot Control register (section Section 4.3.56).
Port n Attention Indicator: See AI_CTL bit field in Slot Control register (section Section 4.3.56).
Port n Attention Push button: See ABP bit field in Slot Status register (section Section 4.3.57).
Port n Manually-Operated Retention Latch (MRL): See MRLSS bit field in Slot Status register (section
Section 4.3.57).
MRLS_DETn
EMIL_CTLn
EMIL_ENGn
I
O
I
Port n Electromechanical Interlock: See EMIL_CTL bit field in Slot Control register (section
Section 4.3.56).
Port n Electromechanical Interlock status: See EMIL_STAT bit field in Slot Status register (section
Section 4.3.57).
Copyright © 2007–2010, Texas Instruments Incorporated
PCI Hot Plug Implementation Overview
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