XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
power-up cycle. The XIO3130 switch asserts PWRONn and because the PWRGDn signal is tied high, the
power-up cycle starts as soon as PWRONn is asserted. After 100 ms, REFCLKn is enabled, and a 100
ms time-out starts. After the 100 ms time-out completes, PERSTn is de-asserted. If the port has been
programmed (see GPIO Control registers in sections Section 4.2.61 through Section 4.2.64) to have a
CLKREQn input when PERSTn de-asserts high, REFCLKn is disabled when CLKREQn is not low.
PWRONn#
PWRGDn
CLKREQn#
REFCLKn
PERSTn#
Unstable
Stable
100 ms
>100 ms
100 ms
Figure 5-3. PCI Hot Plug Power-Up Cycle With No PWGRDn Feedback
5.2.2 Power-Down Cycles
Various conditions cause the assertion of PERSTn, which also cause REFCLKn to stop a short time later.
5.2.2.1 Normal Power-Down
For PCI Hot Plug ports, other conditions may also power-down the port. Software can power the port
down by de-asserting the PC_CTL bit in the Slot Control register. This invokes a normal power-down
cycle, which is the same power-down cycle invoked by the upstream PERST being asserted.
PWRONn#
PWRGDn
CLKREQn#
Stable
REFCLKn
PERSTn#
< 100 ms
Figure 5-4. Normal Power-Down
5.2.2.2 Surprise Removal
Another PCI Hot Plug Port power-down condition occurs when the PRSNTn pin is de-asserted, indicating
that the card or device has been removed without warning (i.e., surprise removal).
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PCI Hot Plug Implementation Overview
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