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NE5532PSE4 参数 Datasheet PDF下载

NE5532PSE4图片预览
型号: NE5532PSE4
PDF下载: 下载PDF文件 查看货源
内容描述: [DUAL OP-AMP, 5000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, PLASTIC, SO-8]
分类和应用: 放大器光电二极管
文件页数/大小: 142 页 / 1062 K
品牌: TI [ TEXAS INSTRUMENTS ]
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XIO3130  
www.ti.com  
SLLS693FMAY 2007REVISED JANUARY 2010  
4.3.47 Next-Item Pointer Register  
The contents of this read-only register indicate the next item in the linked list of capabilities for the  
XIO3130 downstream port. This register reads 00h, which indicates that no additional capabilities are  
supported.  
PCI register offset:  
Register type:  
91h  
Read only  
00h  
Default value:  
BIT NUMBER  
RESET STATE  
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
4.3.48 PCI Express Capabilities Register  
This register indicates the capabilities of the downstream port of the XIO3130 related to PCI Express.  
PCI register offset:  
Register type:  
92h  
Read only  
0061h  
Default value:  
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
Table 4-73. Bit Descriptions – PCI Express Capabilities Register  
BIT  
FIELD NAME  
ACCESS  
DESCRIPTION  
Reserved. When read, these bits return zeros.  
15:14  
RSVD  
r
Interrupt message number. This field is used for MSI support and is implemented as read-only  
zero.  
13:9  
INT_NUM  
r
Slot implemented. This bit indicates whether the port is connected to a slot connector (e.g., for  
PCI Express, ExpressCard™ or other add-in cards). This field can be programmed by writing to  
the General Control register.  
8
SLOT  
r
0 – Port not connected to a slot  
1 – Port connected to a slot  
Device/Port type. This read-only field returns 0110b, which indicates that the device is a  
downstream port of a PCI Express XIO3130.  
7:4  
3:0  
DEV_TYPE  
VERSION  
r
r
Capability version. This field returns 0001b, which indicates revision 1 of the PCI Express  
capability.  
4.3.49 Device Capabilities Register  
The Device Capabilities register indicates the device-specific capabilities of the XIO3130 downstream port.  
PCI register offset:  
Register type:  
94h  
Read Only; Hardware Update  
0000 8XX1h  
Default value:  
BIT NUMBER  
RESET STATE  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER  
RESET STATE  
15  
14  
13  
12  
11  
10  
9
8
7
6
5
4
3
2
1
0
1
0
0
0
u
u
u
v
v
v
0
0
0
0
0
1
Copyright © 2007–2010, Texas Instruments Incorporated  
XIO3130 Configuration Register Space  
107  
Submit Documentation Feedback  
Product Folder Link(s): XIO3130  
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