XIO3130
SLLS693F–MAY 2007–REVISED JANUARY 2010
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Table 4-76. Bit Descriptions – Device Status Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
Reserved. When read, these bits return zeros.
15:6
RSVD
r
Transaction pending. This bit is set when the XIO3130 downstream port has issued a
non-posted transaction that has not been completed yet.
5
PEND
ru
AUX power detected. This bit indicates that AUX power is present. This bit is a direct
reflection of the AUX_PRSNT bit in the Global Chip Control register, and it has the same
default value.
4
APD
ru
0 – No AUX power detected.
1 – AUX power detected.
Unsupported Request detected. This bit is asserted when an Unsupported Request error is
detected (i.e., when a request is received that results in sending a completion with an
Unsupported Request status). Errors are logged in this bit regardless of whether error
reporting is enabled in the Device Control register.
3
URD
rcu
Fatal error detected. This bit is set by the XIO3130 when a fatal error is detected. Errors
are logged in this bit regardless of whether error reporting is enabled in the Device Control
register.
2
1
0
FED
NFED
CED
rcu
rcu
rcu
Nonfatal error detected. This bit is set by the XIO3130 when a nonfatal error is detected.
Errors are logged in this bit regardless of whether error reporting is enabled in the Device
Control register.
Correctable error detected. This bit is set by the XIO3130 when a correctable error is
detected. Errors are logged in this bit regardless of whether error reporting is enabled in
the Device Control register.
4.3.52 Link Capabilities Register
The Link Capabilities register indicates the link-specific capabilities of the XIO3130 downstream port.
PCI register offset:
Register type:
9Ch
Read only
0XXX XC11h
Default value:
BIT NUMBER
RESET STATE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
x
x
0
0
0
w
w
1
y
y
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
y
z
z
z
1
1
0
0
0
0
0
1
0
0
0
1
Table 4-77. Bit Descriptions – Link Capabilities Register
BIT
FIELD NAME
PORT_NUM
RSVD
ACCESS
DESCRIPTION
Port number. This field indicates the port number for the PCI Express link. This field is set to
8’h01 for downstream port 0, 8’h02 for downstream port 1, and 8’h03 for downstream port 2.
31:24
23:21
r
r
Reserved. When read, these bits return zeros.
Data link layer link active reporting capable. This bit indicates whether this slot is capable of
reporting whether the link is active. This field can be programmed by writing to the General
Control register. The default state w is that of the LINK_ACT_RPT_CAP field in the General
Control register.
20
DLL_LARC
r
0 – Incapable of link active reporting
1 – Capable of link active reporting
Surprise down error reporting capable. This bit indicates whether this slot is capable of
detecting and reporting a surprise down error condition. This field can be programmed by
writing to the LINK_ACT_RPT_CAP field in the General Control register. The default state w is
that of the LINK_ACT_RPT_CAP field in the General Control register.
19
18
SDERC
CPM
r
r
0 – Incapable of detecting and reporting a surprise down error condition
1 – Capable of detecting and reporting a surprise down error condition
Clock power management. This bit is 1b, which indicates support for CLKREQ.
110
XIO3130 Configuration Register Space
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