XIO3130
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SLLS693F–MAY 2007–REVISED JANUARY 2010
Table 4-77. Bit Descriptions – Link Capabilities Register (continued)
BIT
FIELD NAME
ACCESS
DESCRIPTION
L1 exit latency. This field indicates the time required to transition from the L1 state to the L0
state. This field is a direct reflection of the Downstream Ports Link PM Latency register
L1_EXIT_LAT field, which is a read/write field that is loaded from EEPROM (if present). The
default value of this field is yyy, which is the same as the default value of the Link PM Latency
register L1_EXIT_LAT field.
17:15
L1_LATENCY
r
L0s exit latency. This field indicates the time required to transition from the L0s state to the L0
state. This field is a direct reflection of the Downstream Ports Link PM Latency register
L0S_EXIT_LAT field, which is a read/write field that is loaded from EEPROM (if present). The
default value of this field is zzz, which is the same as the default value of the Link PM Latency
register L0S_EXIT_LAT field.
14:12
L0S_LATENCY
r
Active State Link PM support. This field reads 11b, which indicates that the XIO3130 supports
both L0s and L1 for Active State Link PM.
11:10
9:4
ASLPMS
MLW
r
r
r
Maximum link width. This field is encoded 000001b to indicate that the XIO3130 downstream
port supports only an x1 PCI Express link.
Maximum link speed. This field is encoded 0001b to indicate that the XIO3130 downstream
port supports a maximum link speed of 2.5 Gb/s.
3:0
MLS
4.3.53 Link Control Register
The Link Control register is used to control link-specific behavior.
PCI register offset:
Register type:
A0h
Read/Write; Read Only
0000h
Default value:
BIT NUMBER
RESET STATE
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-78. Bit Descriptions – Link Control Register
BIT
FIELD NAME
ACCESS
DESCRIPTION
15:9
RSVD
r
Reserved. When read, these bits return zeros.
Clock power management enable. When CLKREQ support is enabled, the EP_LI_LAT field in
the Downstream Ports Link PM Latency register increases due to link PLL locking requirements.
8
CPM_EN
rw
rw
0 – Disables CLKREQ support on downstream port
1 – Enables CLKREQ support on downstream port
Extended synch. This bit is used to force the XIO3130 downstream port to extend the
transmission of FTS ordered sets and an extra TS2 when exiting from L1 before entering to L0.
7
6
ES
0 – Normal synch
1 – Extended synch
Common clock configuration. This bit is set when a common clock is provided to both ends of
the downstream port’s PCI Express link. This bit can be used to change the L0s and L1 exit
latencies.
CCC
rw
0 – Reference clock is asynchronous
1 – Reference clock is synchronous
Retrain link. This bit initiates link retraining on the downstream port. This bit always returns 0b
when read.
5
4
RL
LD
rw
rw
0 – Do not initiate link retraining
1 – Initiate link retraining
Link disable. This bit disables the link. Writes to this bit are immediately reflected in the value
read from the bit, regardless of the actual link state.
0 – Link enabled
1 – Link disabled
Copyright © 2007–2010, Texas Instruments Incorporated
XIO3130 Configuration Register Space
111
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