MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed), the CPU goes
into LPM4 immediately after power-up.
WORD
ADDRESS
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
PRIORITY
Power-Up
External Reset
PORIFG
RSTIFG
Watchdog
Flash Memory
WDTIFG
KEYV
Reset
0xFFFE
15, highest
PC Out--of--Range (see Note 4)
(see Note 1)
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (see Notes 1 and 3)
OFIFG (see Notes 1 and 3)
ACCVIFG (see Notes 1, 2, and 4)
(Non)maskable
(Non)maskable
(Non)maskable
0xFFFC
14
Timer_A5
TA1CCR0 CCIFG0 (see Note 2)
Maskable
0xFFFA
0xFFF8
13
12
TA1CCR1 to TACCR4 CCIFGs,
and TAIFG (see Notes 1 and 2)
Timer_A5
Maskable
Comparator_A+
CAIFG
Maskable
Maskable
0xFFF6
0xFFF4
11
10
Watchdog Timer+
WDTIFG
UCA0RXIFG (see Note 1),
UCB0RXIFG (SPI mode), or
UCB0STAT UCALIFG, UCNACKIFG, UCSTTIFG,
UCSTPIFG (I2C mode)
USCI_A0/B0 Receive
USCI_A0/B0 Transmit
Maskable
0xFFF2
9
(see Note 1)
UCA0TXIFG (see Note 1),
UCB0TXIFG (SPI mode), or
UCB0RXIFG and UCB0TXIFG (I2C mode)
(see Note 1)
Maskable
0xFFF0
8
ADC10
ADC10IFG (see Note 2)
Maskable
Maskable
0xFFEE
0xFFEC
7
6
Timer_A3
TACCR0 CCIFG0 (see Note 2)
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (see Notes 1 and 2)
Timer_A3
Maskable
Maskable
0xFFEA
5
I/O Port P1 (Eight Flags)
P1IFG.0 to P1IFG.7 (see Notes 1 and 2)
0xFFE8
0xFFE6
0xFFE4
0xFFE2
0xFFE0
4
3
2
1
I/O Port P2 (Eight Flags)
Basic Timer1/RTC
P2IFG.0 to P2IFG.7 (see Notes 1 and 2)
BTIFG
Maskable
Maskable
0, lowest
NOTES: 1. Multiple source flags
2. Interrupt flags are located in the module.
3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
4. Access and key violations, KEYV and ACCVIFG.
12
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