MSP430F41x2
MIXED SIGNAL MICROCONTROLLER
SLAS648E -- APRIL 2009 -- REVISED MARCH 2011
interrupt flag register 1 and 2
Address
02h
7
6
5
4
3
2
1
0
NMIIFG
rw--0
RSTIFG
rw--(0)
PORIFG
rw--(1)
OFIFG
rw--1
WDTIFG
rw--(0)
WDTIFG
Set on watchdog timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault
RSTIFG
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset
on VCC power-up.
PORIFG
NMIIFG
Power-on interrupt flag. Set on VCC power--up.
Set via RST/NMI-pin
Address
03h
7
6
5
4
3
2
1
0
UCB0
TXIFG
UCB0
RXIFG
UCA0
TXIFG
UCA0
RXIFG
BTIFG
rw--0
rw--1
rw--0
rw--1
rw--0
UCA0RXIFG USCI_A0 receive interrupt flag
UCA0TXIFG USCI_A0 transmit interrupt flag
UCB0RXIFG USCI_B0 receive interrupt flag
UCB0TXIFG
BTIFG
USCI_B0 transmit interrupt flag
Basic Timer1 interrupt flag
Legend
rw:
Bit can be read and written.
rw-0,1:
rw-(0,1):
Bit can be read and written. It is Reset or set by PUC.
Bit can be read and written. It is Reset or set by POR.
SFR bit is not present in device
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