MSP430F530x, MSP430F5310
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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011
Functional Block Diagram – MSP430F5304IRGZ, MSP430F5304IPT
PA
PB
PC
AVCC AVSS
XIN XOUT
DVCC DVSS VCORE
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x
XT2IN
SYS
REF
ADC10_A
ACLK
Power
Management
I/O Ports
P1/P2
I/O Ports
P4
1×8 I/Os
I/O Ports
P5/P6
1×6 I/Os
1×4 I/Os
Unified
Clock
System
Watchdog
10 Bit
200 KSPS
6KB
8KB
XT2OUT
1×8 I/Os
1×1 I/Os
Interrupt
& Wakeup
PA
SMCLK
Port Map
Control
(P4)
Flash
LDO
SVM/SVS
Brownout
8 Channels
(6 int/ 2 ext)
Window
RAM
MCLK
PB
1×8 I/Os
PC
1×10 I/Os
1×9 I/Os
Comparator
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S:3+1)
USCI0
PU Port
LDO
TA0
TA1
TA2
TB0
JTAG/
SBW
Interface
Ax: UART,
IrDA, SPI
RTC_A
MPY32
CRC16
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
Bx: SPI, I2C
PU.0, PU.1
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