MSP430F530x, MSP430F5310
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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011
Pin Designation – MSP430F5310IZQE, MSP430F5309IZQE, MSP430F5308IZQE
ZQE PACKAGE
(TOP VIEW)
A1
B1
C1
D1
E1
F1
G1
H1
J1
A2
B2
C2
D2
E2
F2
G2
H2
J2
A3
B3
A4
B4
C4
D4
E4
F4
G4
H4
J4
A5
B5
C5
D5
E5
F5
G5
H5
J5
A6
B6
C6
D6
E6
F6
G6
H6
J6
A7
B7
C7
D7
E7
F7
G7
H7
J7
A8
B8
C8
D8
E8
F8
G8
H8
J8
A9
B9
C9
D9
E9
F9
G9
H9
J9
D3
E3
F3
G3
H3
J3
Functional Block Diagram – MSP430F5310IRGZ, MSP430F5309IRGZ, MSP430F5308IRGZ,
MSP430F5310IPT, MSP430F5309IPT, MSP430F5308IPT
PA
PB
PC
AVCC AVSS
XIN XOUT
DVCC DVSS VCORE
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x
XT2IN
SYS
REF
COMP_B
ADC10_A
ACLK
Power
Management
I/O Ports
P1/P2
I/O Ports
P4
1×8 I/Os
I/O Ports
P5/P6
1×6 I/Os
1×4 I/Os
Unified
Clock
System
32KB
24KB
16KB
Watchdog
10 Bit
200 KSPS
6KB
XT2OUT
1×8 I/Os
1×1 I/Os
Interrupt
& Wakeup
PA
SMCLK
Port Map
Control
(P4)
LDO
SVM/SVS
Brownout
8 Channels
(6 ext/ 2 int)
Window
RAM
Flash
MCLK
PB
1×8 I/Os
PC
1×10 I/Os
1×9 I/Os
Comparator
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S:3+1)
USCI0,1
PU Port
LDO
TA0
TA1
TA2
TB0
JTAG/
SBW
Interface
Ax: UART,
IrDA, SPI
RTC_A
MPY32
CRC16
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
Bx: SPI, I2C
PU.0, PU.1
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