MSP430F530x, MSP430F5310
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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011
Functional Block Diagram – MSP430F5310IRGC, MSP430F5309IRGC, MSP430F5308IRG,
MSP430F5310IZQE, MSP430F5309IZQE, MSP430F5308IZQE
PA
PB
PC
AVCC AVSS
XIN XOUT
DVCC DVSS VCORE
RST/NMI
P1.x P2.x P3.x P4.x P5.x P6.x
XT2IN
SYS
REF
COMP_B
ADC10_A
ACLK
Power
Management
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
I/O Ports
P3/P4
1×5 I/Os
1×8 I/Os
I/O Ports
P5/P6
1×6 I/Os
1×8 I/Os
Unified
Clock
System
32KB
24KB
16KB
Watchdog
10 Bit
200 KSPS
6KB
XT2OUT
SMCLK
Port Map
Control
(P4)
LDO
SVM/SVS
Brownout
12 Channels
(10 ext/ 2int)
Window
RAM
Flash
MCLK
PA
1×16 I/Os
PB
1×13 I/Os
PC
1×14 I/Os
Comparator
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S:3+1)
USCI0,1
PU Port
LDO
TA0
TA1
TA2
TB0
JTAG/
SBW
Interface
Ax: UART,
IrDA, SPI
RTC_A
MPY32
CRC16
Timer_A
5 CC
Registers
Timer_A
3 CC
Registers
Timer_A
3 CC
Registers
Timer_B
7 CC
Registers
Bx: SPI, I2C
PU.0, PU.1
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