MSP430F530x, MSP430F5310
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SLAS677B –SEPTEMBER 2010–REVISED MARCH 2011
TA2
TA2 is a 16-bit timer/counter (Timer_A type) with three capture/compare registers. It can support multiple
capture/compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts may
be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 15. TA2 Signal Connections
INPUT PIN NUMBER
DEVICE
INPUT
SIGNAL
MODULE
INPUT
SIGNAL
MODULE
OUTPUT
SIGNAL
DEVICE
OUTPUT
SIGNAL
OUTPUT PIN NUMBER
MODULE
BLOCK
RGC/ZQE
RGZ, PT
RGC/ZQE
RGZ, PT
28/J6-P2.2
TA2CLK
TACLK
ACLK
(internal)
ACLK
Timer
NA
NA
SMCLK
(internal)
SMCLK
28/J6-P2.2
29/H6-P2.3
TA2CLK
TA2.0
DVSS
TACLK
CCI0A
CCI0B
GND
29/H6-P2.3
30/J7-P2.4
CCR0
CCR1
TA0
TA1
TA2.0
TA2.1
DVSS
DVCC
VCC
30/J7-P2.4
31/J8-P2.5
TA2.1
CCI1A
CBOUT
(internal)
CCI1B
DVSS
DVCC
TA2.2
GND
VCC
CCI2A
31/J8-P2.5
ACLK
(internal)
CCI2B
CCR2
TA2
TA2.2
DVSS
DVCC
GND
VCC
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