MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D –JULY 2011–REVISED AUGUST 2012
Functional Block Diagram –
MSP430FR5721IRHA, MSP430FR5725IRHA, MSP430FR5729IRHA,
MSP430FR5731IRHA, MSP430FR5735IRHA, MSP430FR5739IRHA
PA
PB
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x P3.x P4.x
16 KB
(’5739, ’5729)
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3/P4
ACLK
SMCLK
SYS
8 KB
(’5735, ‘5725)
Clock
System
Power
Management
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1 KB
Boot
ROM
4 KB
(’5731, ‘5721)
Watchdog
REF
Interrupt
& Wakeup
PA
SVS
FRAM
RAM
MCLK
Memory
Protection
Unit
1×16 I/Os
1×10 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
eUSCI_A0: eUSCI_A1:
UART,
IrDA, SPI
TA0
TA1
TB0
TB1
TB2
ADC10_B
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
10 Bit
200KSPS
Comp_D
RTC_B
MPY32
CRC
eUSCI_B0:
SPI, I2C
(2) Timer_A (3) Timer_B
3 CC
Registers
16 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
3 CC
Registers
16 channels
(12 ext/2 int)
Functional Block Diagram –
MSP430FR5723IRHA, MSP430FR5727IRHA,
MSP430FR5733IRHA, MSP430FR5737IRHA
PA
PB
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x P3.x P4.x
16 KB
(’5737, ’5727)
I/O Ports
P1/P2
2×8 I/Os
I/O Ports
P3/P4
ACLK
SMCLK
SYS
8 KB
(’5733, ‘5723)
Clock
System
Power
Management
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1 KB
Boot
ROM
Watchdog
Interrupt
& Wakeup
PA
SVS
FRAM
RAM
MCLK
Memory
Protection
Unit
1×16 I/Os
1×10 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
TB0
TB1
TB2
eUSCI_A0:
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
eUSCI_A1:
UART,
IrDA, SPI
Comp_D
RTC_B
MPY32
CRC
REF
(2) Timer_A (3) Timer_B
3 CC
Registers
16 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
eUSCI_B0:
SPI, I2C
3 CC
Registers
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