MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
Functional Block Diagram –
MSP430FR5721IRHA, MSP430FR5725IRHA, MSP430FR5729IRHA,
MSP430FR5731IRHA, MSP430FR5735IRHA, MSP430FR5739IRHA
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE
AVCC AVSS
P1.x
PA
P2.x
P3.x
PB
P4.x
16 KB
Clock
System
ACLK
SMCLK
(’5739, ’5729)
8 KB
(’5735, ‘5725)
4 KB
(’5731, ‘5721)
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
REF
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
FRAM
MCLK
Memory
Protection
Unit
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1×10 I/Os
CPUXV2
and
Working
Registers
MAB
MDB
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
MPY32
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
TB0
TB1
TB2
RTC_B
CRC
eUSCI_B0:
SPI, I2C
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_A1:
UART,
IrDA, SPI
ADC10_B
10 Bit
200KSPS
16 channels
(12 ext/2 int)
Comp_D
16 channels
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
Functional Block Diagram –
MSP430FR5723IRHA, MSP430FR5727IRHA,
MSP430FR5733IRHA, MSP430FR5737IRHA
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE
AVCC AVSS
P1.x
PA
P2.x
P3.x
PB
P4.x
16 KB
Clock
System
ACLK
SMCLK
FRAM
MCLK
Memory
Protection
Unit
(’5737, ’5727)
8 KB
(’5733, ‘5723)
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
I/O Ports
P1/P2
2×8 I/Os
Interrupt
& Wakeup
PA
1×16 I/Os
I/O Ports
P3/P4
1×8 I/Os
1x 2 I/Os
Interrupt
& Wakeup
PB
1×10 I/Os
CPUXV2
and
Working
Registers
MAB
MDB
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
MPY32
(2) Timer_A
3 CC
Registers
(3) Timer_B
3 CC
Registers
TB0
TB1
TB2
RTC_B
CRC
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
eUSCI_A1:
UART,
IrDA, SPI
Comp_D
REF
16 channels
Copyright © 2011–2012, Texas Instruments Incorporated
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