MSP430FR573x
MSP430FR572x
SLAS639D – JULY 2011 – REVISED AUGUST 2012
Functional Block Diagram –
MSP430FR5720IRGE, MSP430FR5724IRGE, MSP430FR5728IRGE,
MSP430FR5730IRGE, MSP430FR5734IRGE, MSP430FR5738IRGE
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE
AVCC AVSS
P1.x
PA
P2.x
16 KB
Clock
System
ACLK
SMCLK
(’5738, ’5728)
8 KB
(’5734, ‘5724)
4 KB
(’5730, ‘5720)
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
REF
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
Interrupt
& Wakeup
PA
1×11 I/Os
FRAM
MCLK
Memory
Protection
Unit
CPUXV2
and
Working
Registers
MAB
MDB
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
MPY32
(2) Timer_A
3 CC
Registers
(1) Timer_B
3 CC
Registers
TB0
RTC_B
eUSCI_A0:
UART,
IrDA, SPI
CRC
eUSCI_B0:
SPI, I2C
ADC10_B
10 Bit
200KSPS
8 channels
(6 ext/2 int)
Comp_D
10 channels
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
Functional Block Diagram –
MSP430FR5722IRGE, MSP430FR5726IRGE,
MSP430FR5732IRGE, MSP430FR5736IRGE
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE
AVCC AVSS
P1.x
PA
P2.x
16 KB
Clock
System
ACLK
SMCLK
FRAM
MCLK
Memory
Protection
Unit
(’5736, ’5726)
8 KB
(’5732, ‘5722)
1 KB
RAM
Boot
ROM
Power
Management
SVS
SYS
Watchdog
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
Interrupt
& Wakeup
PA
1×11 I/Os
CPUXV2
and
Working
Registers
MAB
MDB
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
MPY32
(2) Timer_A
3 CC
Registers
(1) Timer_B
3 CC
Registers
TB0
RTC_B
eUSCI_A0:
UART,
IrDA, SPI
eUSCI_B0:
SPI, I2C
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
JTAG/
SBW
Interface
Comp_D
REF
10 channels
CRC
Copyright © 2011–2012, Texas Instruments Incorporated
9
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