MSP430FR573x
MSP430FR572x
www.ti.com
SLAS639D –JULY 2011–REVISED AUGUST 2012
Functional Block Diagram –
MSP430FR5720IRGE, MSP430FR5724IRGE, MSP430FR5728IRGE,
MSP430FR5730IRGE, MSP430FR5734IRGE, MSP430FR5738IRGE
PA
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x
16 KB
(’5738, ’5728)
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
ACLK
SMCLK
SYS
8 KB
(’5734, ‘5724)
Clock
System
Power
Management
1 KB
Boot
ROM
4 KB
(’5730, ‘5720)
Watchdog
REF
SVS
Interrupt
& Wakeup
PA
FRAM
RAM
MCLK
Memory
Protection
Unit
1×11 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
eUSCI_A0:
UART,
IrDA, SPI
TA0
TA1
TB0
ADC10_B
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
10 Bit
200KSPS
Comp_D
RTC_B
MPY32
CRC
eUSCI_B0:
SPI, I2C
(2) Timer_A (1) Timer_B
3 CC
Registers
10 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
3 CC
Registers
8 channels
(6 ext/2 int)
Functional Block Diagram –
MSP430FR5722IRGE, MSP430FR5726IRGE,
MSP430FR5732IRGE, MSP430FR5736IRGE
PA
PJ.4/XIN
PJ.5/XOUT
DVCC DVSS VCORE AVCC AVSS
P1.x P2.x
16 KB
(’5736, ’5726)
I/O Ports
P1/P2
1×8 I/Os
1×3 I/Os
ACLK
SMCLK
SYS
8 KB
(’5732, ‘5722)
Clock
System
Power
Management
1 KB
Boot
ROM
Watchdog
SVS
Interrupt
& Wakeup
PA
FRAM
RAM
MCLK
Memory
Protection
Unit
1×11 I/Os
MAB
MDB
CPUXV2
and
Working
Registers
DMA
3 Channel
EEM
(S: 3+1)
TA0
TA1
TB0
eUSCI_A0:
UART,
IrDA, SPI
RST/NMI/SBWTDIO
TEST/SBWTCK
PJ.0/TDO
JTAG/
SBW
Interface
Comp_D
RTC_B
MPY32
CRC
REF
(2) Timer_A (1) Timer_B
3 CC
Registers
10 channels
PJ.1/TDI/TCLK
PJ.2/TMS
PJ.3/TCK
eUSCI_B0:
SPI, I2C
3 CC
Registers
Copyright © 2011–2012, Texas Instruments Incorporated
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